mirror of
https://github.com/qmk/qmk_firmware
synced 2024-11-16 08:56:11 +00:00
8e8803459f
* Initial Ducky One 2 Mini keyboard and keymap
* Keymap macro issue, together with general polish suggestions
* Separate default keymap into proper default, iso and ansi versions
* info.json updates (Configurator support). DEBOUNCE define adjust.
* Unused keymap defines removed.
* update requested ducky one mini2 board changes
* ducky: don't trigger app key with left shift
* ducky: make default mouse key behavior more linear
* ducky: add GRAVE_ESC_GUI_OVERRIDE to allow for win+esc to work
* ducky: playpause on fn space
* ducky: disable RGB_MATRIX until driver is merged
* ducky: clang-format matrix and one2mini.c
* ducky: update requested changes
Remove WFI_IDLE since it's already in the rules.mk CORTEX_ENABLE_WFI_IDLE=TRUE
* ducky: update requested changes
* ducky: move winkey grave esc to default keymap
* ducky: remove dipswitch from keymap and use DIP_SWITCH_MATRIX_GRID instead
* ducky: info.json lint
* ducky: enable DIP_SWITCH_ENABLE rule
* ducky: update readme
* ducky: fix backslash on default keymap
* ducky: remove unused USB_LED_CAPSLOCK_INDEX 28
* ducky: move mbi5042 led driver to ducky keyboard
* ducky: cosmetics
* ducky: requested changes
* ducky: refactor matrix.c again so we can better compare it to other boards
* ducky: remove bootmagic_lite as the boards bootloader trigger is actually handled in its own bootloader
* ducky: remove custom matrix
* ducky: update for chibios-contrib changes
* ducky: debug new USB driver
* ducky: debug usb issues
* ducky: update chibios version
* ducky: remove halconf.h
* ducky: update rules.mk
* ducky: update chconf.h
* Matching submodules.
* Restructure to explicitly define which board is in use, remove RGB driver pending followup PR.
* Revert "Matching submodules."
This reverts commit 2fbb34e0c6.
Co-authored-by: GitWellBack <48095880+GitWellBack@users.noreply.github.com>
Co-authored-by: Nick Brassel <nick@tzarc.org>
961 lines
58 KiB
C
961 lines
58 KiB
C
/*
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ChibiOS Driver element - Copyright (C) 2019 /u/KeepItUnder
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef BOARD_H
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#define BOARD_H
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/*
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* Setup for Generic NUC123 board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_NUC123SD4AN0
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#define BOARD_NAME "Nuvoton NUC123SD4AN0 MCU"
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/*
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* Board oscillators-related settings.
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* NOTE: LSE not fitted.
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* NOTE: HSE is fitted.
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*/
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#if !defined(NUC123_LSECLK)
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#define NUC123_LSECLK 0U
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#endif
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#define NUC123_LSEDRV (3U << 3U)
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#if !defined(NUC123_HSECLK)
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#define NUC123_HSECLK 12000000U
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#endif
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//#define NUC123_HSE_BYPASS
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/*
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* MCU type as defined in the NUC123 header.
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*/
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#define NUC123SD4AN0
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/*
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* GPIO Multi Function Pin USB Setup
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* Requires Some GPIO pins to be disabled/set to USB
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*/
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/*
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* IO pins assignments.
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*/
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#define GPIOA_PIN0 0U
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#define GPIOA_PIN1 1U
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#define GPIOA_PIN2 2U
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#define GPIOA_PIN3 3U
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#define GPIOA_PIN4 4U
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#define GPIOA_PIN5 5U
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#define GPIOA_PIN6 6U
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#define GPIOA_PIN7 7U
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#define GPIOA_PIN8 8U
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#define GPIOA_PIN9 9U
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#define GPIOA_SPI1_MISO0 10U
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#define GPIOA_SPI1_CLK 11U
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#define GPIOA_PWM0 12U
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#define GPIOA_PWM1 13U
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#define GPIOA_PWM2 14U
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#define GPIOA_PWM3 15U
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#define GPIOB_UART0_RXD 0U
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#define GPIOB_UART0_TXD 1U
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#define GPIOB_UART0_RTS 2U
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#define GPIOB_UART0_CTS 3U
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#define GPIOB_UART1_RXD 4U
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#define GPIOB_UART1_TXD 5U
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#define GPIOB_UART1_RTS 6U
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#define GPIOB_UART1_CTS 7U
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#define GPIOB_TM0 8U
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#define GPIOB_TM1 9U
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#define GPIOB_TM2 10U
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#define GPIOB_PIN11 11U
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#define GPIOB_CLK0 12U
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#define GPIOB_PIN13 13U
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#define GPIOB_INT0 14U
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#define GPIOB_INT1 15U
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#define GPIOC_PIN0 0U
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#define GPIOC_PIN1 1U
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#define GPIOC_PIN2 2U
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#define GPIOC_PIN3 3U
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#define GPIOC_PIN4 4U
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#define GPIOC_PIN5 5U
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#define GPIOC_PIN6 6U
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#define GPIOC_PIN7 7U
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#define GPIOC_PIN8 8U
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#define GPIOC_PIN9 9U
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#define GPIOC_PIN10 10U
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#define GPIOC_PIN11 11U
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#define GPIOC_PIN12 12U
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#define GPIOC_PIN13 13U
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#define GPIOC_PIN14 14U
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#define GPIOC_PIN15 15U
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#define GPIOD_ADC0 0U
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#define GPIOD_ADC1 1U
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#define GPIOD_ADC2 2U
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#define GPIOD_ADC3 3U
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#define GPIOD_ADC4 4U
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#define GPIOD_ADC5 5U
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#define GPIOD_PIN6 6U
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#define GPIOD_PIN7 7U
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#define GPIOD_PIN8 8U
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#define GPIOD_PIN9 9U
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#define GPIOD_PIN10 10U
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#define GPIOD_PIN11 11U
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#define GPIOD_PIN12 12U
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#define GPIOD_PIN13 13U
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#define GPIOD_PIN14 14U
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#define GPIOD_PIN15 15U
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#define GPIOE_PIN0 0U
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#define GPIOE_PIN1 1U
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#define GPIOE_PIN2 2U
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#define GPIOE_PIN3 3U
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#define GPIOE_PIN4 4U
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#define GPIOE_PIN5 5U
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#define GPIOE_PIN6 6U
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#define GPIOE_PIN7 7U
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#define GPIOE_PIN8 8U
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#define GPIOE_PIN9 9U
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#define GPIOE_PIN10 10U
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#define GPIOE_PIN11 11U
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#define GPIOE_PIN12 12U
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#define GPIOE_PIN13 13U
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#define GPIOE_PIN14 14U
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#define GPIOE_PIN15 15U
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#define GPIOF_OSC_OUT 0U
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#define GPIOF_OSC_IN 1U
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#define GPIOF_I2C0_SDA 2U
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#define GPIOF_I2C0_SCL 3U
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#define GPIOF_PIN4 4U
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#define GPIOF_PIN5 5U
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#define GPIOF_PIN6 6U
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#define GPIOF_PIN7 7U
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#define GPIOF_PIN8 8U
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#define GPIOF_PIN9 9U
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#define GPIOF_PIN10 10U
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#define GPIOF_PIN11 11U
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#define GPIOF_PIN12 12U
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#define GPIOF_PIN13 13U
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#define GPIOF_PIN14 14U
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#define GPIOF_PIN15 15U
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/*
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* IO lines assignments.
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*/
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#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
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#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
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#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
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#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
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// #define LINE_SPI2_SCK PAL_LINE(GPIOB, 13U)
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// #define LINE_SPI2_MISO PAL_LINE(GPIOB, 14U)
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// #define LINE_SPI2_MOSI PAL_LINE(GPIOB, 15U)
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#define LINE_OSC_IN PAL_LINE(GPIOF, 0U)
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#define LINE_OSC_OUT PAL_LINE(GPIOF, 1U)
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the NUC123 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
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#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
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#define PIN_MODE_OPENDRAIN(n) (2U << ((n) * 2U))
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#define PIN_MODE_QUASI(n) (3U << ((n) * 2U))
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#define PIN_DIGITAL_EN(n) (0U << (n))
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#define PIN_DIGITAL_DIS(n) (1U << (n))
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#define PIN_DMASK_DIS(n) (0U << (n))
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#define PIN_DMASK_EN(n) (1U << (n))
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#define PIN_DBNCE_DIS(n) (0U << (n))
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#define PIN_DBNCE_EN(n) (1U << (n))
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#define PIN_IMD_EDGE(n) (0U << (n))
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#define PIN_IMD_LVL(n) (1U << (n))
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#define PIN_IEN_FELL_DIS(n) (0U << (n))
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#define PIN_IEN_FELL_EN(n) (1U << (n))
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#define PIN_IEN_REHL_DIS(n) ((0U << (n)) << 16)
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#define PIN_IEN_REHL_EN(n) ((1U << (n)) << 16)
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#define PIN_ISRC_EN(n) (1U << (n))
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#define PIN_ISRC_DIS(n) (0U << (n))
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#define PIN_ISRC_CLR(n) (1U << (n))
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#define PIN_DATA_LOW(n) (0U << (n))
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#define PIN_DATA_HIGH(n) (1U << (n))
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/*
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* GPIOA setup:
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*
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* PA0 - PIN0 (input pullup).
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* PA1 - PIN1 (input pullup).
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* PA2 - PIN2 (input pullup).
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* PA3 - PIN3 (input pullup).
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* PA4 - PIN4 (input pullup).
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* PA5 - PIN5 (input pullup).
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* PA6 - PIN6 (input pullup).
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* PA7 - PIN7 (input pullup).
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* PA8 - PIN8 (input pullup).
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* PA9 - PIN9 (input pullup).
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* PA10 - SPI1_MISO0 (input pullup).
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* PA11 - SPI1_CLK (input floating).
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* PA12 - PWM0 (input floating).
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* PA13 - PWM1 (input pullup).
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* PA14 - PWM2 (input pullup).
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* PA15 - PWM3 (input pullup).
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*/
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#define VAL_GPIOA_PMD (PIN_MODE_INPUT(GPIOA_PIN0) | \
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PIN_MODE_INPUT(GPIOA_PIN1) | \
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PIN_MODE_INPUT(GPIOA_PIN2) | \
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PIN_MODE_INPUT(GPIOA_PIN3) | \
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PIN_MODE_INPUT(GPIOA_PIN4) | \
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PIN_MODE_INPUT(GPIOA_PIN5) | \
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PIN_MODE_INPUT(GPIOA_PIN6) | \
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PIN_MODE_INPUT(GPIOA_PIN7) | \
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PIN_MODE_INPUT(GPIOA_PIN8) | \
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PIN_MODE_INPUT(GPIOA_PIN9) | \
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PIN_MODE_INPUT(GPIOA_SPI1_MISO0) | \
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PIN_MODE_INPUT(GPIOA_SPI1_CLK) | \
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PIN_MODE_INPUT(GPIOA_PWM0) | \
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PIN_MODE_INPUT(GPIOA_PWM1) | \
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PIN_MODE_INPUT(GPIOA_PWM2) | \
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PIN_MODE_INPUT(GPIOA_PWM3))
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#define VAL_GPIOA_OFFD (PIN_DIGITAL_EN(GPIOA_PIN0) | \
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PIN_DIGITAL_EN(GPIOA_PIN1) | \
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PIN_DIGITAL_EN(GPIOA_PIN2) | \
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PIN_DIGITAL_EN(GPIOA_PIN3) | \
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PIN_DIGITAL_EN(GPIOA_PIN4) | \
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PIN_DIGITAL_EN(GPIOA_PIN5) | \
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PIN_DIGITAL_EN(GPIOA_PIN6) | \
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PIN_DIGITAL_EN(GPIOA_PIN7) | \
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PIN_DIGITAL_EN(GPIOA_PIN8) | \
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PIN_DIGITAL_EN(GPIOA_PIN9) | \
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PIN_DIGITAL_EN(GPIOA_SPI1_MISO0) | \
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PIN_DIGITAL_EN(GPIOA_SPI1_CLK) | \
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PIN_DIGITAL_EN(GPIOA_PWM0) | \
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PIN_DIGITAL_EN(GPIOA_PWM1) | \
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PIN_DIGITAL_EN(GPIOA_PWM2) | \
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PIN_DIGITAL_EN(GPIOA_PWM3))
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#define VAL_GPIOA_DMASK (PIN_DMASK_EN(GPIOA_PIN0) | \
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PIN_DMASK_EN(GPIOA_PIN1) | \
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PIN_DMASK_EN(GPIOA_PIN2) | \
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PIN_DMASK_EN(GPIOA_PIN3) | \
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PIN_DMASK_EN(GPIOA_PIN4) | \
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PIN_DMASK_EN(GPIOA_PIN5) | \
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PIN_DMASK_EN(GPIOA_PIN6) | \
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PIN_DMASK_EN(GPIOA_PIN7) | \
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PIN_DMASK_EN(GPIOA_PIN8) | \
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PIN_DMASK_EN(GPIOA_PIN9) | \
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PIN_DMASK_EN(GPIOA_SPI1_MISO0) | \
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PIN_DMASK_EN(GPIOA_SPI1_CLK) | \
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PIN_DMASK_EN(GPIOA_PWM0) | \
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PIN_DMASK_EN(GPIOA_PWM1) | \
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PIN_DMASK_EN(GPIOA_PWM2) | \
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PIN_DMASK_EN(GPIOA_PWM3))
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#define VAL_GPIOA_DBEN (PIN_DBNCE_EN(GPIOA_PIN0) | \
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PIN_DBNCE_EN(GPIOA_PIN1) | \
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PIN_DBNCE_EN(GPIOA_PIN2) | \
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PIN_DBNCE_EN(GPIOA_PIN3) | \
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PIN_DBNCE_EN(GPIOA_PIN4) | \
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PIN_DBNCE_EN(GPIOA_PIN5) | \
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PIN_DBNCE_EN(GPIOA_PIN6) | \
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PIN_DBNCE_EN(GPIOA_PIN7) | \
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PIN_DBNCE_EN(GPIOA_PIN8) | \
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PIN_DBNCE_EN(GPIOA_PIN9) | \
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PIN_DBNCE_EN(GPIOA_SPI1_MISO0) | \
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PIN_DBNCE_EN(GPIOA_SPI1_CLK) | \
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PIN_DBNCE_EN(GPIOA_PWM0) | \
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PIN_DBNCE_EN(GPIOA_PWM1) | \
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PIN_DBNCE_EN(GPIOA_PWM2) | \
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PIN_DBNCE_EN(GPIOA_PWM3))
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#define VAL_GPIOA_IMD (PIN_IMD_EDGE(GPIOA_PIN0) | \
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PIN_IMD_EDGE(GPIOA_PIN1) | \
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PIN_IMD_EDGE(GPIOA_PIN2) | \
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PIN_IMD_EDGE(GPIOA_PIN3) | \
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PIN_IMD_EDGE(GPIOA_PIN4) | \
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PIN_IMD_EDGE(GPIOA_PIN5) | \
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PIN_IMD_EDGE(GPIOA_PIN6) | \
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PIN_IMD_EDGE(GPIOA_PIN7) | \
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PIN_IMD_EDGE(GPIOA_PIN8) | \
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PIN_IMD_EDGE(GPIOA_PIN9) | \
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PIN_IMD_EDGE(GPIOA_SPI1_MISO0) | \
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PIN_IMD_EDGE(GPIOA_SPI1_CLK) | \
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PIN_IMD_EDGE(GPIOA_PWM0) | \
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PIN_IMD_EDGE(GPIOA_PWM1) | \
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PIN_IMD_EDGE(GPIOA_PWM2) | \
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PIN_IMD_EDGE(GPIOA_PWM3))
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#define VAL_GPIOA_IEN (PIN_IEN_FELL_DIS(GPIOA_PIN0) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN1) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN2) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN3) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN4) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN5) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN6) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN7) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN8) | \
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PIN_IEN_FELL_DIS(GPIOA_PIN9) | \
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PIN_IEN_FELL_DIS(GPIOA_SPI1_MISO0) | \
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PIN_IEN_FELL_DIS(GPIOA_SPI1_CLK) | \
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PIN_IEN_FELL_DIS(GPIOA_PWM0) | \
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PIN_IEN_FELL_DIS(GPIOA_PWM1) | \
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PIN_IEN_FELL_DIS(GPIOA_PWM2) | \
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PIN_IEN_FELL_DIS(GPIOA_PWM3))
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#define VAL_GPIOA_ISRC (PIN_ISRC_DIS(GPIOA_PIN0) | \
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PIN_ISRC_DIS(GPIOA_PIN1) | \
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PIN_ISRC_DIS(GPIOA_PIN2) | \
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PIN_ISRC_DIS(GPIOA_PIN3) | \
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PIN_ISRC_DIS(GPIOA_PIN4) | \
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PIN_ISRC_DIS(GPIOA_PIN5) | \
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PIN_ISRC_DIS(GPIOA_PIN6) | \
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PIN_ISRC_DIS(GPIOA_PIN7) | \
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PIN_ISRC_DIS(GPIOA_PIN8) | \
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PIN_ISRC_DIS(GPIOA_PIN9) | \
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PIN_ISRC_DIS(GPIOA_SPI1_MISO0) | \
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PIN_ISRC_DIS(GPIOA_SPI1_CLK) | \
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PIN_ISRC_DIS(GPIOA_PWM0) | \
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PIN_ISRC_DIS(GPIOA_PWM1) | \
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PIN_ISRC_DIS(GPIOA_PWM2) | \
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PIN_ISRC_DIS(GPIOA_PWM3))
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#define VAL_GPIOA_DOUT (PIN_DATA_LOW(GPIOA_PIN0) | \
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PIN_DATA_LOW(GPIOA_PIN1) | \
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PIN_DATA_LOW(GPIOA_PIN2) | \
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PIN_DATA_LOW(GPIOA_PIN3) | \
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PIN_DATA_LOW(GPIOA_PIN4) | \
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PIN_DATA_LOW(GPIOA_PIN5) | \
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PIN_DATA_LOW(GPIOA_PIN6) | \
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PIN_DATA_LOW(GPIOA_PIN7) | \
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PIN_DATA_LOW(GPIOA_PIN8) | \
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PIN_DATA_LOW(GPIOA_PIN9) | \
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PIN_DATA_LOW(GPIOA_SPI1_MISO0) | \
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PIN_DATA_LOW(GPIOA_SPI1_CLK) | \
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PIN_DATA_LOW(GPIOA_PWM0) | \
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PIN_DATA_LOW(GPIOA_PWM1) | \
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PIN_DATA_LOW(GPIOA_PWM2) | \
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PIN_DATA_LOW(GPIOA_PWM3))
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/*
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* GPIOB setup:
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*
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* PB0 - UART0_RXD (input pullup).
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* PB1 - UART0_TXD (output).
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* PB2 - UART0_RTS (output).
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* PB3 - UART0_CTS (output).
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* PB4 - UART1_RXD (output).
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* PB5 - UART1_TXD (output).
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* PB6 - UART1_RTS (output).
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* PB7 - UART1_CTS (output).
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* PB8 - TM0 (input pullup).
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* PB9 - TM1 (input pullup).
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* PB10 - TM2 (input pullup).
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* PB11 - PIN11 (input pullup).
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* PB12 - CLK0 (output).
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* PB13 - PIN13 (output).
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* PB14 - INT0 (debug output).
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* PB15 - INT1 (input pullup).
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*/
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#define VAL_GPIOB_PMD (PIN_MODE_INPUT(GPIOB_UART0_RXD) | \
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PIN_MODE_OUTPUT(GPIOB_UART0_TXD) | \
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PIN_MODE_OUTPUT(GPIOB_UART0_RTS) | \
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PIN_MODE_OUTPUT(GPIOB_UART0_CTS) | \
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PIN_MODE_OUTPUT(GPIOB_UART1_RXD) | \
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PIN_MODE_OUTPUT(GPIOB_UART1_TXD) | \
|
|
PIN_MODE_OUTPUT(GPIOB_UART1_RTS) | \
|
|
PIN_MODE_OUTPUT(GPIOB_UART1_CTS) | \
|
|
PIN_MODE_INPUT(GPIOB_TM0) | \
|
|
PIN_MODE_INPUT(GPIOB_TM1) | \
|
|
PIN_MODE_INPUT(GPIOB_TM2) | \
|
|
PIN_MODE_INPUT(GPIOB_PIN11) | \
|
|
PIN_MODE_OUTPUT(GPIOB_CLK0) | \
|
|
PIN_MODE_OUTPUT(GPIOB_PIN13) | \
|
|
PIN_MODE_OUTPUT(GPIOB_INT0) | \
|
|
PIN_MODE_INPUT(GPIOB_INT1))
|
|
#define VAL_GPIOB_OFFD (PIN_DIGITAL_EN(GPIOB_UART0_RXD) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART0_TXD) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART0_RTS) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART0_CTS) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART1_RXD) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART1_TXD) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART1_RTS) | \
|
|
PIN_DIGITAL_DIS(GPIOB_UART1_CTS) | \
|
|
PIN_DIGITAL_DIS(GPIOB_TM0) | \
|
|
PIN_DIGITAL_EN(GPIOB_TM1) | \
|
|
PIN_DIGITAL_EN(GPIOB_TM2) | \
|
|
PIN_DIGITAL_EN(GPIOB_PIN11) | \
|
|
PIN_DIGITAL_DIS(GPIOB_CLK0) | \
|
|
PIN_DIGITAL_DIS(GPIOB_PIN13) | \
|
|
PIN_DIGITAL_DIS(GPIOB_INT0) | \
|
|
PIN_DIGITAL_EN(GPIOB_INT1))
|
|
#define VAL_GPIOB_DMASK (PIN_DMASK_EN(GPIOB_UART0_RXD) | \
|
|
PIN_DMASK_DIS(GPIOB_UART0_TXD) | \
|
|
PIN_DMASK_DIS(GPIOB_UART0_RTS) | \
|
|
PIN_DMASK_DIS(GPIOB_UART0_CTS) | \
|
|
PIN_DMASK_DIS(GPIOB_UART1_RXD) | \
|
|
PIN_DMASK_DIS(GPIOB_UART1_TXD) | \
|
|
PIN_DMASK_DIS(GPIOB_UART1_RTS) | \
|
|
PIN_DMASK_DIS(GPIOB_UART1_CTS) | \
|
|
PIN_DMASK_EN(GPIOB_TM0) | \
|
|
PIN_DMASK_EN(GPIOB_TM1) | \
|
|
PIN_DMASK_EN(GPIOB_TM2) | \
|
|
PIN_DMASK_EN(GPIOB_PIN11) | \
|
|
PIN_DMASK_DIS(GPIOB_CLK0) | \
|
|
PIN_DMASK_DIS(GPIOB_PIN13) | \
|
|
PIN_DMASK_DIS(GPIOB_INT0) | \
|
|
PIN_DMASK_EN(GPIOB_INT1))
|
|
#define VAL_GPIOB_DBEN (PIN_DBNCE_EN(GPIOB_UART0_RXD) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART0_TXD) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART0_RTS) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART0_CTS) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART1_RXD) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART1_TXD) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART1_RTS) | \
|
|
PIN_DBNCE_DIS(GPIOB_UART1_CTS) | \
|
|
PIN_DBNCE_EN(GPIOB_TM0) | \
|
|
PIN_DBNCE_EN(GPIOB_TM1) | \
|
|
PIN_DBNCE_EN(GPIOB_TM2) | \
|
|
PIN_DBNCE_EN(GPIOB_PIN11) | \
|
|
PIN_DBNCE_DIS(GPIOB_CLK0) | \
|
|
PIN_DBNCE_DIS(GPIOB_PIN13) | \
|
|
PIN_DBNCE_DIS(GPIOB_INT0) | \
|
|
PIN_DBNCE_EN(GPIOB_INT1))
|
|
#define VAL_GPIOB_IMD (PIN_IMD_EDGE(GPIOB_UART0_RXD) | \
|
|
PIN_IMD_EDGE(GPIOB_UART0_TXD) | \
|
|
PIN_IMD_EDGE(GPIOB_UART0_RTS) | \
|
|
PIN_IMD_EDGE(GPIOB_UART0_CTS) | \
|
|
PIN_IMD_EDGE(GPIOB_UART1_RXD) | \
|
|
PIN_IMD_EDGE(GPIOB_UART1_TXD) | \
|
|
PIN_IMD_EDGE(GPIOB_UART1_RTS) | \
|
|
PIN_IMD_EDGE(GPIOB_UART1_CTS) | \
|
|
PIN_IMD_EDGE(GPIOB_TM0) | \
|
|
PIN_IMD_EDGE(GPIOB_TM1) | \
|
|
PIN_IMD_EDGE(GPIOB_TM2) | \
|
|
PIN_IMD_EDGE(GPIOB_PIN11) | \
|
|
PIN_IMD_EDGE(GPIOB_CLK0) | \
|
|
PIN_IMD_EDGE(GPIOB_PIN13) | \
|
|
PIN_IMD_EDGE(GPIOB_INT0) | \
|
|
PIN_IMD_EDGE(GPIOB_INT1))
|
|
#define VAL_GPIOB_IEN (PIN_IEN_FELL_DIS(GPIOB_UART0_RXD) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART0_TXD) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART0_RTS) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART0_CTS) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART1_RXD) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART1_TXD) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART1_RTS) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_UART1_CTS) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_TM0) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_TM1) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_TM2) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_PIN11) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_CLK0) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_PIN13) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_INT0) | \
|
|
PIN_IEN_FELL_DIS(GPIOB_INT1))
|
|
#define VAL_GPIOB_ISRC (PIN_ISRC_DIS(GPIOB_UART0_RXD) | \
|
|
PIN_ISRC_DIS(GPIOB_UART0_TXD) | \
|
|
PIN_ISRC_DIS(GPIOB_UART0_RTS) | \
|
|
PIN_ISRC_DIS(GPIOB_UART0_CTS) | \
|
|
PIN_ISRC_DIS(GPIOB_UART1_RXD) | \
|
|
PIN_ISRC_DIS(GPIOB_UART1_TXD) | \
|
|
PIN_ISRC_DIS(GPIOB_UART1_RTS) | \
|
|
PIN_ISRC_DIS(GPIOB_UART1_CTS) | \
|
|
PIN_ISRC_DIS(GPIOB_TM0) | \
|
|
PIN_ISRC_DIS(GPIOB_TM1) | \
|
|
PIN_ISRC_DIS(GPIOB_TM2) | \
|
|
PIN_ISRC_DIS(GPIOB_PIN11) | \
|
|
PIN_ISRC_DIS(GPIOB_CLK0) | \
|
|
PIN_ISRC_DIS(GPIOB_PIN13) | \
|
|
PIN_ISRC_DIS(GPIOB_INT0) | \
|
|
PIN_ISRC_DIS(GPIOB_INT1))
|
|
#define VAL_GPIOB_DOUT (PIN_DATA_LOW(GPIOB_UART0_RXD) | \
|
|
PIN_DATA_LOW(GPIOB_UART0_TXD) | \
|
|
PIN_DATA_LOW(GPIOB_UART0_RTS) | \
|
|
PIN_DATA_LOW(GPIOB_UART0_CTS) | \
|
|
PIN_DATA_LOW(GPIOB_UART1_RXD) | \
|
|
PIN_DATA_LOW(GPIOB_UART1_TXD) | \
|
|
PIN_DATA_LOW(GPIOB_UART1_RTS) | \
|
|
PIN_DATA_LOW(GPIOB_UART1_CTS) | \
|
|
PIN_DATA_LOW(GPIOB_TM0) | \
|
|
PIN_DATA_LOW(GPIOB_TM1) | \
|
|
PIN_DATA_LOW(GPIOB_TM2) | \
|
|
PIN_DATA_LOW(GPIOB_PIN11) | \
|
|
PIN_DATA_LOW(GPIOB_CLK0) | \
|
|
PIN_DATA_LOW(GPIOB_PIN13) | \
|
|
PIN_DATA_LOW(GPIOB_INT0) | \
|
|
PIN_DATA_LOW(GPIOB_INT1))
|
|
|
|
/*
|
|
* GPIOC setup:
|
|
*
|
|
* PC0 - PIN0 (input pullup).
|
|
* PC1 - PIN1 (input pullup).
|
|
* PC2 - PIN2 (input pullup).
|
|
* PC3 - PIN3 (input pullup).
|
|
* PC4 - PIN4 (output).
|
|
* PC5 - PIN5 (output).
|
|
* PC6 - PIN6 (input pullup).
|
|
* PC7 - PIN7 (input pullup).
|
|
* PC8 - PIN8 (input pullup).
|
|
* PC9 - PIN9 (input pullup).
|
|
* PC10 - PIN10 (input pullup).
|
|
* PC11 - PIN11 (input pullup).
|
|
* PC12 - PIN12 (input pullup).
|
|
* PC13 - PIN13 (input pullup).
|
|
* PC14 - PIN14 (input pullup).
|
|
* PC15 - PIN15 (input pullup).
|
|
*/
|
|
#define VAL_GPIOC_PMD (PIN_MODE_INPUT(GPIOC_PIN0) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN1) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN2) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN3) | \
|
|
PIN_MODE_OUTPUT(GPIOC_PIN4) | \
|
|
PIN_MODE_OUTPUT(GPIOC_PIN5) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN6) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN7) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN8) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN9) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN10) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN11) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN12) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN13) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN14) | \
|
|
PIN_MODE_INPUT(GPIOC_PIN15))
|
|
#define VAL_GPIOC_OFFD (PIN_DIGITAL_EN(GPIOC_PIN0) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN1) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN2) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN3) | \
|
|
PIN_DIGITAL_DIS(GPIOC_PIN4) | \
|
|
PIN_DIGITAL_DIS(GPIOC_PIN5) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN6) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN7) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN8) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN9) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN10) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN11) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN12) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN13) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN14) | \
|
|
PIN_DIGITAL_EN(GPIOC_PIN15))
|
|
#define VAL_GPIOC_DMASK (PIN_DMASK_EN(GPIOC_PIN0) | \
|
|
PIN_DMASK_EN(GPIOC_PIN1) | \
|
|
PIN_DMASK_EN(GPIOC_PIN2) | \
|
|
PIN_DMASK_EN(GPIOC_PIN3) | \
|
|
PIN_DMASK_DIS(GPIOC_PIN4) | \
|
|
PIN_DMASK_DIS(GPIOC_PIN5) | \
|
|
PIN_DMASK_EN(GPIOC_PIN6) | \
|
|
PIN_DMASK_EN(GPIOC_PIN7) | \
|
|
PIN_DMASK_EN(GPIOC_PIN8) | \
|
|
PIN_DMASK_EN(GPIOC_PIN9) | \
|
|
PIN_DMASK_EN(GPIOC_PIN10) | \
|
|
PIN_DMASK_EN(GPIOC_PIN11) | \
|
|
PIN_DMASK_EN(GPIOC_PIN12) | \
|
|
PIN_DMASK_EN(GPIOC_PIN13) | \
|
|
PIN_DMASK_EN(GPIOC_PIN14) | \
|
|
PIN_DMASK_EN(GPIOC_PIN15))
|
|
#define VAL_GPIOC_DBEN (PIN_DBNCE_EN(GPIOC_PIN0) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN1) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN2) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN3) | \
|
|
PIN_DBNCE_DIS(GPIOC_PIN4) | \
|
|
PIN_DBNCE_DIS(GPIOC_PIN5) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN6) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN7) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN8) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN9) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN10) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN11) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN12) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN13) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN14) | \
|
|
PIN_DBNCE_EN(GPIOC_PIN15))
|
|
#define VAL_GPIOC_IMD (PIN_IMD_EDGE(GPIOC_PIN0) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN1) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN2) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN3) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN4) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN5) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN6) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN7) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN8) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN9) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN10) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN11) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN12) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN13) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN14) | \
|
|
PIN_IMD_EDGE(GPIOC_PIN15))
|
|
#define VAL_GPIOC_IEN (PIN_IEN_FELL_DIS(GPIOC_PIN0) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN1) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN2) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN3) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN4) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN5) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN6) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN7) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN8) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN9) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN10) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN11) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN12) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN13) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN14) | \
|
|
PIN_IEN_FELL_DIS(GPIOC_PIN15))
|
|
#define VAL_GPIOC_ISRC (PIN_ISRC_DIS(GPIOC_PIN0) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN1) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN2) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN3) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN4) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN5) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN6) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN7) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN8) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN9) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN10) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN11) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN12) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN13) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN14) | \
|
|
PIN_ISRC_DIS(GPIOC_PIN15))
|
|
#define VAL_GPIOC_DOUT (PIN_DATA_LOW(GPIOC_PIN0) | \
|
|
PIN_DATA_LOW(GPIOC_PIN1) | \
|
|
PIN_DATA_LOW(GPIOC_PIN2) | \
|
|
PIN_DATA_LOW(GPIOC_PIN3) | \
|
|
PIN_DATA_LOW(GPIOC_PIN4) | \
|
|
PIN_DATA_LOW(GPIOC_PIN5) | \
|
|
PIN_DATA_LOW(GPIOC_PIN6) | \
|
|
PIN_DATA_LOW(GPIOC_PIN7) | \
|
|
PIN_DATA_LOW(GPIOC_PIN8) | \
|
|
PIN_DATA_LOW(GPIOC_PIN9) | \
|
|
PIN_DATA_LOW(GPIOC_PIN10) | \
|
|
PIN_DATA_LOW(GPIOC_PIN11) | \
|
|
PIN_DATA_LOW(GPIOC_PIN12) | \
|
|
PIN_DATA_LOW(GPIOC_PIN13) | \
|
|
PIN_DATA_LOW(GPIOC_PIN14) | \
|
|
PIN_DATA_LOW(GPIOC_PIN15))
|
|
|
|
/*
|
|
* GPIOD setup:
|
|
*
|
|
* PD0 - ADC0 (input pullup).
|
|
* PD1 - ADC1 (input pullup).
|
|
* PD2 - ADC2 (input pullup).
|
|
* PD3 - ADC3 (output).
|
|
* PD4 - ADC4 (output).
|
|
* PD5 - ADC5 (output).
|
|
* PD6 - PIN6 (input pullup).
|
|
* PD7 - PIN7 (input pullup).
|
|
* PD8 - PIN8 (input pullup).
|
|
* PD9 - PIN9 (output).
|
|
* PD10 - PIN10 (debug output).
|
|
* PD11 - PIN11 (output).
|
|
* PD12 - PIN12 (input pullup).
|
|
* PD13 - PIN13 (input pullup).
|
|
* PD14 - PIN14 (input pullup).
|
|
* PD15 - PIN15 (input pullup).
|
|
*/
|
|
#define VAL_GPIOD_PMD (PIN_MODE_INPUT(GPIOD_ADC0) | \
|
|
PIN_MODE_INPUT(GPIOD_ADC1) | \
|
|
PIN_MODE_INPUT(GPIOD_ADC2) | \
|
|
PIN_MODE_OUTPUT(GPIOD_ADC3) | \
|
|
PIN_MODE_OUTPUT(GPIOD_ADC4) | \
|
|
PIN_MODE_OUTPUT(GPIOD_ADC5) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN6) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN7) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN8) | \
|
|
PIN_MODE_OUTPUT(GPIOD_PIN9) | \
|
|
PIN_MODE_OUTPUT(GPIOD_PIN10) | \
|
|
PIN_MODE_OUTPUT(GPIOD_PIN11) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN12) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN13) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN14) | \
|
|
PIN_MODE_INPUT(GPIOD_PIN15))
|
|
#define VAL_GPIOD_OFFD (PIN_DIGITAL_EN(GPIOD_ADC0) | \
|
|
PIN_DIGITAL_EN(GPIOD_ADC1) | \
|
|
PIN_DIGITAL_EN(GPIOD_ADC2) | \
|
|
PIN_DIGITAL_DIS(GPIOD_ADC3) | \
|
|
PIN_DIGITAL_DIS(GPIOD_ADC4) | \
|
|
PIN_DIGITAL_DIS(GPIOD_ADC5) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN6) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN7) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN8) | \
|
|
PIN_DIGITAL_DIS(GPIOD_PIN9) | \
|
|
PIN_DIGITAL_DIS(GPIOD_PIN10) | \
|
|
PIN_DIGITAL_DIS(GPIOD_PIN11) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN12) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN13) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN14) | \
|
|
PIN_DIGITAL_EN(GPIOD_PIN15))
|
|
#define VAL_GPIOD_DMASK (PIN_DMASK_EN(GPIOD_ADC0) | \
|
|
PIN_DMASK_EN(GPIOD_ADC1) | \
|
|
PIN_DMASK_EN(GPIOD_ADC2) | \
|
|
PIN_DMASK_DIS(GPIOD_ADC3) | \
|
|
PIN_DMASK_DIS(GPIOD_ADC4) | \
|
|
PIN_DMASK_DIS(GPIOD_ADC5) | \
|
|
PIN_DMASK_EN(GPIOD_PIN6) | \
|
|
PIN_DMASK_EN(GPIOD_PIN7) | \
|
|
PIN_DMASK_EN(GPIOD_PIN8) | \
|
|
PIN_DMASK_DIS(GPIOD_PIN9) | \
|
|
PIN_DMASK_DIS(GPIOD_PIN10) | \
|
|
PIN_DMASK_DIS(GPIOD_PIN11) | \
|
|
PIN_DMASK_EN(GPIOD_PIN12) | \
|
|
PIN_DMASK_EN(GPIOD_PIN13) | \
|
|
PIN_DMASK_EN(GPIOD_PIN14) | \
|
|
PIN_DMASK_EN(GPIOD_PIN15))
|
|
#define VAL_GPIOD_DBEN (PIN_DBNCE_EN(GPIOD_ADC0) | \
|
|
PIN_DBNCE_EN(GPIOD_ADC1) | \
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PIN_DBNCE_EN(GPIOD_ADC2) | \
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PIN_DBNCE_DIS(GPIOD_ADC3) | \
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PIN_DBNCE_DIS(GPIOD_ADC4) | \
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PIN_DBNCE_DIS(GPIOD_ADC5) | \
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PIN_DBNCE_EN(GPIOD_PIN6) | \
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PIN_DBNCE_EN(GPIOD_PIN7) | \
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PIN_DBNCE_EN(GPIOD_PIN8) | \
|
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PIN_DBNCE_DIS(GPIOD_PIN9) | \
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PIN_DBNCE_DIS(GPIOD_PIN10) | \
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PIN_DBNCE_DIS(GPIOD_PIN11) | \
|
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PIN_DBNCE_EN(GPIOD_PIN12) | \
|
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PIN_DBNCE_EN(GPIOD_PIN13) | \
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PIN_DBNCE_EN(GPIOD_PIN14) | \
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PIN_DBNCE_EN(GPIOD_PIN15))
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#define VAL_GPIOD_IMD (PIN_IMD_EDGE(GPIOD_ADC0) | \
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PIN_IMD_EDGE(GPIOD_ADC1) | \
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PIN_IMD_EDGE(GPIOD_ADC2) | \
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PIN_IMD_EDGE(GPIOD_ADC3) | \
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PIN_IMD_EDGE(GPIOD_ADC4) | \
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PIN_IMD_EDGE(GPIOD_ADC5) | \
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PIN_IMD_EDGE(GPIOD_PIN6) | \
|
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PIN_IMD_EDGE(GPIOD_PIN7) | \
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PIN_IMD_EDGE(GPIOD_PIN8) | \
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PIN_IMD_EDGE(GPIOD_PIN9) | \
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PIN_IMD_EDGE(GPIOD_PIN10) | \
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PIN_IMD_EDGE(GPIOD_PIN11) | \
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PIN_IMD_EDGE(GPIOD_PIN12) | \
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PIN_IMD_EDGE(GPIOD_PIN13) | \
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PIN_IMD_EDGE(GPIOD_PIN14) | \
|
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PIN_IMD_EDGE(GPIOD_PIN15))
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#define VAL_GPIOD_IEN (PIN_IEN_FELL_DIS(GPIOD_ADC0) | \
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PIN_IEN_FELL_DIS(GPIOD_ADC1) | \
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PIN_IEN_FELL_DIS(GPIOD_ADC2) | \
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PIN_IEN_FELL_DIS(GPIOD_ADC3) | \
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PIN_IEN_FELL_DIS(GPIOD_ADC4) | \
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PIN_IEN_FELL_DIS(GPIOD_ADC5) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN6) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN7) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN8) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN9) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN10) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN11) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN12) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN13) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN14) | \
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PIN_IEN_FELL_DIS(GPIOD_PIN15))
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#define VAL_GPIOD_ISRC (PIN_ISRC_DIS(GPIOD_ADC0) | \
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PIN_ISRC_DIS(GPIOD_ADC1) | \
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PIN_ISRC_DIS(GPIOD_ADC2) | \
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PIN_ISRC_DIS(GPIOD_ADC3) | \
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PIN_ISRC_DIS(GPIOD_ADC4) | \
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|
PIN_ISRC_DIS(GPIOD_ADC5) | \
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|
PIN_ISRC_DIS(GPIOD_PIN6) | \
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PIN_ISRC_DIS(GPIOD_PIN7) | \
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PIN_ISRC_DIS(GPIOD_PIN8) | \
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|
PIN_ISRC_DIS(GPIOD_PIN9) | \
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|
PIN_ISRC_DIS(GPIOD_PIN10) | \
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|
PIN_ISRC_DIS(GPIOD_PIN11) | \
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|
PIN_ISRC_DIS(GPIOD_PIN12) | \
|
|
PIN_ISRC_DIS(GPIOD_PIN13) | \
|
|
PIN_ISRC_DIS(GPIOD_PIN14) | \
|
|
PIN_ISRC_DIS(GPIOD_PIN15))
|
|
#define VAL_GPIOD_DOUT (PIN_DATA_LOW(GPIOD_ADC0) | \
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|
PIN_DATA_LOW(GPIOD_ADC1) | \
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PIN_DATA_LOW(GPIOD_ADC2) | \
|
|
PIN_DATA_LOW(GPIOD_ADC3) | \
|
|
PIN_DATA_LOW(GPIOD_ADC4) | \
|
|
PIN_DATA_LOW(GPIOD_ADC5) | \
|
|
PIN_DATA_LOW(GPIOD_PIN6) | \
|
|
PIN_DATA_LOW(GPIOD_PIN7) | \
|
|
PIN_DATA_LOW(GPIOD_PIN8) | \
|
|
PIN_DATA_LOW(GPIOD_PIN9) | \
|
|
PIN_DATA_LOW(GPIOD_PIN10) | \
|
|
PIN_DATA_LOW(GPIOD_PIN11) | \
|
|
PIN_DATA_LOW(GPIOD_PIN12) | \
|
|
PIN_DATA_LOW(GPIOD_PIN13) | \
|
|
PIN_DATA_LOW(GPIOD_PIN14) | \
|
|
PIN_DATA_LOW(GPIOD_PIN15))
|
|
|
|
/*
|
|
* GPIOF setup:
|
|
*
|
|
* PF0 - OSC_IN (input floating).
|
|
* PF1 - OSC_OUT (input floating).
|
|
* PF2 - I2C0_SDA (input pullup).
|
|
* PF3 - I2C0_SCL (input pullup).
|
|
* PF4 - PIN4 (input pullup).
|
|
* PF5 - PIN5 (input pullup).
|
|
* PF6 - PIN6 (input pullup).
|
|
* PF7 - PIN7 (input pullup).
|
|
* PF8 - PIN8 (input pullup).
|
|
* PF9 - PIN9 (input pullup).
|
|
* PF10 - PIN10 (input pullup).
|
|
* PF11 - PIN11 (input pullup).
|
|
* PF12 - PIN12 (input pullup).
|
|
* PF13 - PIN13 (input pullup).
|
|
* PF14 - PIN14 (input pullup).
|
|
* PF15 - PIN15 (input pullup).
|
|
*/
|
|
#define VAL_GPIOF_PMD (PIN_MODE_QUASI(GPIOF_OSC_IN) | \
|
|
PIN_MODE_QUASI(GPIOF_OSC_OUT) | \
|
|
PIN_MODE_INPUT(GPIOF_I2C0_SDA) | \
|
|
PIN_MODE_INPUT(GPIOF_I2C0_SCL) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN4) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN5) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN6) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN7) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN8) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN9) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN10) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN11) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN12) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN13) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN14) | \
|
|
PIN_MODE_INPUT(GPIOF_PIN15))
|
|
#define VAL_GPIOF_OFFD (PIN_DIGITAL_DIS(GPIOF_OSC_IN) | \
|
|
PIN_DIGITAL_DIS(GPIOF_OSC_OUT) | \
|
|
PIN_DIGITAL_EN(GPIOF_I2C0_SDA) | \
|
|
PIN_DIGITAL_EN(GPIOF_I2C0_SCL) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN4) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN5) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN6) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN7) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN8) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN9) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN10) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN11) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN12) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN13) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN14) | \
|
|
PIN_DIGITAL_EN(GPIOF_PIN15))
|
|
#define VAL_GPIOF_DMASK (PIN_DMASK_DIS(GPIOF_OSC_IN) | \
|
|
PIN_DMASK_DIS(GPIOF_OSC_OUT) | \
|
|
PIN_DMASK_EN(GPIOF_I2C0_SDA) | \
|
|
PIN_DMASK_EN(GPIOF_I2C0_SCL) | \
|
|
PIN_DMASK_EN(GPIOF_PIN4) | \
|
|
PIN_DMASK_EN(GPIOF_PIN5) | \
|
|
PIN_DMASK_EN(GPIOF_PIN6) | \
|
|
PIN_DMASK_EN(GPIOF_PIN7) | \
|
|
PIN_DMASK_EN(GPIOF_PIN8) | \
|
|
PIN_DMASK_EN(GPIOF_PIN9) | \
|
|
PIN_DMASK_EN(GPIOF_PIN10) | \
|
|
PIN_DMASK_EN(GPIOF_PIN11) | \
|
|
PIN_DMASK_EN(GPIOF_PIN12) | \
|
|
PIN_DMASK_EN(GPIOF_PIN13) | \
|
|
PIN_DMASK_EN(GPIOF_PIN14) | \
|
|
PIN_DMASK_EN(GPIOF_PIN15))
|
|
#define VAL_GPIOF_DBEN (PIN_DBNCE_DIS(GPIOF_OSC_IN) | \
|
|
PIN_DBNCE_DIS(GPIOF_OSC_OUT) | \
|
|
PIN_DBNCE_EN(GPIOF_I2C0_SDA) | \
|
|
PIN_DBNCE_EN(GPIOF_I2C0_SCL) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN4) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN5) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN6) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN7) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN8) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN9) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN10) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN11) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN12) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN13) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN14) | \
|
|
PIN_DBNCE_EN(GPIOF_PIN15))
|
|
#define VAL_GPIOF_IMD (PIN_IMD_LVL(GPIOF_OSC_IN) | \
|
|
PIN_IMD_LVL(GPIOF_OSC_OUT) | \
|
|
PIN_IMD_EDGE(GPIOF_I2C0_SDA) | \
|
|
PIN_IMD_EDGE(GPIOF_I2C0_SCL) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN4) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN5) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN6) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN7) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN8) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN9) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN10) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN11) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN12) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN13) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN14) | \
|
|
PIN_IMD_EDGE(GPIOF_PIN15))
|
|
#define VAL_GPIOF_IEN (PIN_IEN_FELL_DIS(GPIOF_OSC_IN) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_OSC_OUT) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_I2C0_SDA) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_I2C0_SCL) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN4) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN5) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN6) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN7) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN8) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN9) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN10) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN11) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN12) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN13) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN14) | \
|
|
PIN_IEN_FELL_DIS(GPIOF_PIN15))
|
|
#define VAL_GPIOF_ISRC (PIN_ISRC_DIS(GPIOF_OSC_IN) | \
|
|
PIN_ISRC_DIS(GPIOF_OSC_OUT) | \
|
|
PIN_ISRC_DIS(GPIOF_I2C0_SDA) | \
|
|
PIN_ISRC_DIS(GPIOF_I2C0_SCL) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN4) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN5) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN6) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN7) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN8) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN9) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN10) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN11) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN12) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN13) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN14) | \
|
|
PIN_ISRC_DIS(GPIOF_PIN15))
|
|
#define VAL_GPIOF_DOUT (PIN_DATA_LOW(GPIOF_OSC_IN) | \
|
|
PIN_DATA_LOW(GPIOF_OSC_OUT) | \
|
|
PIN_DATA_LOW(GPIOF_I2C0_SDA) | \
|
|
PIN_DATA_LOW(GPIOF_I2C0_SCL) | \
|
|
PIN_DATA_LOW(GPIOF_PIN4) | \
|
|
PIN_DATA_LOW(GPIOF_PIN5) | \
|
|
PIN_DATA_LOW(GPIOF_PIN6) | \
|
|
PIN_DATA_LOW(GPIOF_PIN7) | \
|
|
PIN_DATA_LOW(GPIOF_PIN8) | \
|
|
PIN_DATA_LOW(GPIOF_PIN9) | \
|
|
PIN_DATA_LOW(GPIOF_PIN10) | \
|
|
PIN_DATA_LOW(GPIOF_PIN11) | \
|
|
PIN_DATA_LOW(GPIOF_PIN12) | \
|
|
PIN_DATA_LOW(GPIOF_PIN13) | \
|
|
PIN_DATA_LOW(GPIOF_PIN14) | \
|
|
PIN_DATA_LOW(GPIOF_PIN15))
|
|
|
|
|
|
#if !defined(_FROM_ASM_)
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
void boardInit(void);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* _FROM_ASM_ */
|
|
|
|
#endif /* BOARD_H */
|