mirror of
https://github.com/openstenoproject/qmk
synced 2024-11-14 12:34:39 +00:00
37932c293c
* Update split_common to use standard i2c drivers * Eliminate RGB_DIRTY/BACKLIT_DIRTY * Fix avr i2c_master error handling * Fix i2c_slave addressing * Remove unneeded timeout on i2c_stop() * Fix RGB I2C transfers * Remove incorrect comment
71 lines
No EOL
2.1 KiB
C
Executable file
71 lines
No EOL
2.1 KiB
C
Executable file
/* Library made by: g4lvanix
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* Github repository: https://github.com/g4lvanix/I2C-slave-lib
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*/
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#include <avr/io.h>
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#include <util/twi.h>
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#include <avr/interrupt.h>
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#include <stdbool.h>
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#include "i2c_slave.h"
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volatile uint8_t i2c_slave_reg[I2C_SLAVE_REG_COUNT];
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static volatile uint8_t buffer_address;
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static volatile bool slave_has_register_set = false;
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void i2c_slave_init(uint8_t address){
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// load address into TWI address register
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TWAR = address;
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// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
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TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN);
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}
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void i2c_slave_stop(void){
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// clear acknowledge and enable bits
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TWCR &= ~((1 << TWEA) | (1 << TWEN));
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}
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ISR(TWI_vect){
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uint8_t ack = 1;
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switch(TW_STATUS){
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case TW_SR_SLA_ACK:
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// The device is now a slave receiver
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slave_has_register_set = false;
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break;
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case TW_SR_DATA_ACK:
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// This device is a slave receiver and has received data
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// First byte is the location then the bytes will be writen in buffer with auto-incriment
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if(!slave_has_register_set){
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buffer_address = TWDR;
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if (buffer_address >= I2C_SLAVE_REG_COUNT) { // address out of bounds dont ack
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ack = 0;
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buffer_address = 0;
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}
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slave_has_register_set = true; // address has been receaved now fill in buffer
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} else {
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i2c_slave_reg[buffer_address] = TWDR;
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buffer_address++;
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}
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break;
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case TW_ST_SLA_ACK:
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case TW_ST_DATA_ACK:
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// This device is a slave transmitter and master has requested data
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TWDR = i2c_slave_reg[buffer_address];
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buffer_address++;
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break;
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case TW_BUS_ERROR:
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// We got an error, reset i2c
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TWCR = 0;
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default:
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break;
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}
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// Reset i2c state machine to be ready for next interrupt
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TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN);
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} |