mirror of
https://github.com/openstenoproject/qmk
synced 2024-11-16 13:34:44 +00:00
5477bf39bf
* add hhkb bluetooth functionality (rn42) pretty much straight from tmk some minor changes to make things work * hhkb jp personal keymap * Revert "hhkb jp personal keymap" This reverts commit 886713d8bb98572f03110f285706a8140a083892.
156 lines
3.7 KiB
ArmAsm
156 lines
3.7 KiB
ArmAsm
;---------------------------------------------------------------------------;
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; Software implemented UART module ;
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; (C)ChaN, 2005 (http://elm-chan.org/) ;
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;---------------------------------------------------------------------------;
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; Bit rate settings:
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;
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; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz
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; 2.4kbps 138 - - - - - - - -
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; 4.8kbps 68 138 - - - - - - -
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; 9.6kbps 33 68 138 208 - - - - -
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; 19.2kbps - 33 68 102 138 173 208 - -
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; 38.4kbps - - 33 50 68 85 102 138 172
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; 57.6kbps - - 21 33 44 56 68 91 114
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; 115.2kbps - - - - 21 27 33 44 56
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.nolist
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#include <avr/io.h>
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.list
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#define BPS 44 /* Bit delay. (see above table) */
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#define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
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#define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */
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#define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */
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#define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */
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#define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */
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#ifdef SPM_PAGESIZE
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.macro _LPMI reg
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lpm \reg, Z+
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.endm
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.macro _MOVW dh,dl, sh,sl
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movw \dl, \sl
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.endm
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#else
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.macro _LPMI reg
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lpm
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mov \reg, r0
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adiw ZL, 1
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.endm
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.macro _MOVW dh,dl, sh,sl
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mov \dl, \sl
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mov \dh, \sh
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.endm
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#endif
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;---------------------------------------------------------------------------;
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; Transmit a byte in serial format of N81
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;
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;Prototype: void xmit (uint8_t data);
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;Size: 16 words
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.global xmit
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.func xmit
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xmit:
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#if BIDIR
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ldi r23, BPS-1 ;Pre-idle time for bidirectional data line
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5: dec r23 ;
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brne 5b ;/
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#endif
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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com r24 ;C = start bit
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ldi r25, 10 ;Bit counter
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cli ;Start critical section
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1: ldi r23, BPS-1 ;----- Bit transferring loop
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2: dec r23 ;Wait for a bit time
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brne 2b ;/
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brcs 3f ;MISO = bit to be sent
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OUT_1 ;
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3: brcc 4f ;
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OUT_0 ;/
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4: lsr r24 ;Get next bit into C
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dec r25 ;All bits sent?
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brne 1b ; no, coutinue
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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;---------------------------------------------------------------------------;
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; Receive a byte
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;
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;Prototype: uint8_t rcvr (void);
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;Size: 19 words
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.global rcvr
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.func rcvr
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rcvr:
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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ldi r24, 0x80 ;Receiving shift reg
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cli ;Start critical section
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1: SKIP_IN_1 ;Wait for idle
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rjmp 1b
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2: SKIP_IN_0 ;Wait for start bit
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rjmp 2b
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ldi r25, BPS/2 ;Wait for half bit time
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3: dec r25
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brne 3b
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4: ldi r25, BPS ;----- Bit receiving loop
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5: dec r25 ;Wait for a bit time
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brne 5b ;/
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lsr r24 ;Next bit
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SKIP_IN_0 ;Get a data bit into r24.7
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ori r24, 0x80
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brcc 4b ;All bits received? no, continue
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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; Not wait for start bit. This should be called after detecting start bit.
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.global recv
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.func recv
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recv:
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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ldi r24, 0x80 ;Receiving shift reg
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cli ;Start critical section
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;1: SKIP_IN_1 ;Wait for idle
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; rjmp 1b
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;2: SKIP_IN_0 ;Wait for start bit
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; rjmp 2b
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ldi r25, BPS/2 ;Wait for half bit time
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3: dec r25
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brne 3b
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4: ldi r25, BPS ;----- Bit receiving loop
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5: dec r25 ;Wait for a bit time
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brne 5b ;/
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lsr r24 ;Next bit
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SKIP_IN_0 ;Get a data bit into r24.7
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ori r24, 0x80
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brcc 4b ;All bits received? no, continue
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ldi r25, BPS/2 ;Wait for half bit time
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6: dec r25
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brne 6b
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7: SKIP_IN_1 ;Wait for stop bit
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rjmp 7b
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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