mirror of
https://github.com/openstenoproject/qmk
synced 2024-11-11 02:59:09 +00:00
d2ff66a985
* include variables and .h files as pp directives * start layout compilation * split ergodoxes up * don't compile all layouts for everything * might seg fault * reset layouts variable * actually reset layouts * include rules.mk instead * remove includes from rules.mk * update variable setting * load visualizer from path * adds some more examples * adds more layouts * more boards added * more boards added * adds documentation for layouts * use lowercase names for LAYOUT_ * add layout.json files for each layout * add community folder, default keymaps for layouts * touch-up default layouts * touch-up layouts, some keyboard rules.mk * update documentation for layouts * fix up serial/i2c switches
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#define ST7565_LCD_BIAS ST7565_LCD_BIAS_9 // actually 6
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#define ST7565_ADC ST7565_ADC_NORMAL
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#define ST7565_COM_SCAN ST7565_COM_SCAN_DEC
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#define ST7565_PAGE_ORDER 0,1,2,3
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/*
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* Custom page order for several LCD boards, e.g. HEM12864-99
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* #define ST7565_PAGE_ORDER 4,5,6,7,0,1,2,3
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*/
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#define ST7565_GPIOPORT GPIOC
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#define ST7565_PORT PORTC
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#define ST7565_A0_PIN 7
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#define ST7565_RST_PIN 8
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#define ST7565_MOSI_PIN 6
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#define ST7565_SLCK_PIN 5
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#define ST7565_SS_PIN 4
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#define palSetPadModeRaw(portname, bits) \
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ST7565_PORT->PCR[ST7565_##portname##_PIN] = bits
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#define palSetPadModeNamed(portname, portmode) \
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palSetPadMode(ST7565_GPIOPORT, ST7565_##portname##_PIN, portmode)
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#define ST7565_SPI_MODE PORTx_PCRn_DSE | PORTx_PCRn_MUX(2)
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// DSPI Clock and Transfer Attributes
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// Frame Size: 8 bits
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// MSB First
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// CLK Low by default
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static const SPIConfig spi1config = {
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// Operation complete callback or @p NULL.
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.end_cb = NULL,
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//The chip select line port - when not using pcs.
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.ssport = ST7565_GPIOPORT,
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// brief The chip select line pad number - when not using pcs.
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.sspad=ST7565_SS_PIN,
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// SPI initialization data.
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.tar0 =
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SPIx_CTARn_FMSZ(7) // Frame size = 8 bytes
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| SPIx_CTARn_ASC(1) // After SCK Delay Scaler (min 50 ns) = 55.56ns
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| SPIx_CTARn_DT(0) // Delay After Transfer Scaler (no minimum)= 27.78ns
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| SPIx_CTARn_CSSCK(0) // PCS to SCK Delay Scaler (min 20 ns) = 27.78ns
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| SPIx_CTARn_PBR(0) // Baud Rate Prescaler = 2
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| SPIx_CTARn_BR(0) // Baud rate (min 50ns) = 55.56ns
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};
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static GFXINLINE void acquire_bus(GDisplay *g) {
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(void) g;
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// Only the LCD is using the SPI bus, so no need to acquire
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// spiAcquireBus(&SPID1);
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spiSelect(&SPID1);
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}
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static GFXINLINE void release_bus(GDisplay *g) {
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(void) g;
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// Only the LCD is using the SPI bus, so no need to release
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//spiReleaseBus(&SPID1);
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spiUnselect(&SPID1);
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}
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static GFXINLINE void init_board(GDisplay *g) {
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(void) g;
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palSetPadModeNamed(A0, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPad(ST7565_GPIOPORT, ST7565_A0_PIN);
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palSetPadModeNamed(RST, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPad(ST7565_GPIOPORT, ST7565_RST_PIN);
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palSetPadModeRaw(MOSI, ST7565_SPI_MODE);
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palSetPadModeRaw(SLCK, ST7565_SPI_MODE);
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palSetPadModeNamed(SS, PAL_MODE_OUTPUT_PUSHPULL);
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spiInit();
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spiStart(&SPID1, &spi1config);
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release_bus(g);
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}
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static GFXINLINE void post_init_board(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void setpin_reset(GDisplay *g, bool_t state) {
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(void) g;
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if (state) {
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palClearPad(ST7565_GPIOPORT, ST7565_RST_PIN);
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}
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else {
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palSetPad(ST7565_GPIOPORT, ST7565_RST_PIN);
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}
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}
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static GFXINLINE void enter_data_mode(GDisplay *g) {
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palSetPad(ST7565_GPIOPORT, ST7565_A0_PIN);
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}
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static GFXINLINE void enter_cmd_mode(GDisplay *g) {
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palClearPad(ST7565_GPIOPORT, ST7565_A0_PIN);
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}
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static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
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(void) g;
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spiSend(&SPID1, length, data);
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}
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#endif /* _GDISP_LLD_BOARD_H */
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