forked from mirrors/qmk_firmware
271 lines
9.5 KiB
C
271 lines
9.5 KiB
C
/* Copyright 2017 Jason Williams
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* Copyright 2018 Jack Humbert
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* Copyright 2018 Yiancar
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* Copyright 2020 MelGeek
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "is31fl3741.h"
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#include <string.h>
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#include "i2c_master.h"
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#include "wait.h"
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#define IS31FL3741_COMMANDREGISTER 0xFD
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#define IS31FL3741_COMMANDREGISTER_WRITELOCK 0xFE
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#define IS31FL3741_INTERRUPTMASKREGISTER 0xF0
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#define IS31FL3741_INTERRUPTSTATUSREGISTER 0xF1
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#define IS31FL3741_IDREGISTER 0xFC
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#define IS31FL3741_PAGE_PWM0 0x00 // PG0
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#define IS31FL3741_PAGE_PWM1 0x01 // PG1
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#define IS31FL3741_PAGE_SCALING_0 0x02 // PG2
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#define IS31FL3741_PAGE_SCALING_1 0x03 // PG3
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#define IS31FL3741_PAGE_FUNCTION 0x04 // PG4
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#define IS31FL3741_REG_CONFIGURATION 0x00 // PG4
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#define IS31FL3741_REG_GLOBALCURRENT 0x01 // PG4
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#define IS31FL3741_REG_PULLDOWNUP 0x02 // PG4
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#define IS31FL3741_REG_PWM_FREQUENCY 0x36 // PG4
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#define IS31FL3741_REG_RESET 0x3F // PG4
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#ifndef IS31FL3741_I2C_TIMEOUT
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# define IS31FL3741_I2C_TIMEOUT 100
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#endif
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#ifndef IS31FL3741_I2C_PERSISTENCE
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# define IS31FL3741_I2C_PERSISTENCE 0
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#endif
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#ifndef IS31FL3741_CONFIGURATION
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# define IS31FL3741_CONFIGURATION 0x01
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#endif
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#ifndef IS31FL3741_PWM_FREQUENCY
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# define IS31FL3741_PWM_FREQUENCY IS31FL3741_PWM_FREQUENCY_29K_HZ
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#endif
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#ifndef IS31FL3741_SWPULLUP
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# define IS31FL3741_SWPULLUP IS31FL3741_PUR_32KR
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#endif
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#ifndef IS31FL3741_CSPULLUP
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# define IS31FL3741_CSPULLUP IS31FL3741_PUR_32KR
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#endif
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#ifndef IS31FL3741_GLOBALCURRENT
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# define IS31FL3741_GLOBALCURRENT 0xFF
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#endif
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#define IS31FL3741_MAX_LEDS 351
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// Transfer buffer for TWITransmitData()
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uint8_t g_twi_transfer_buffer[20] = {0xFF};
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// These buffers match the IS31FL3741 and IS31FL3741A PWM registers.
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// The scaling buffers match the PG2 and PG3 LED On/Off registers.
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// Storing them like this is optimal for I2C transfers to the registers.
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// We could optimize this and take out the unused registers from these
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// buffers and the transfers in is31fl3741_write_pwm_buffer() but it's
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// probably not worth the extra complexity.
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uint8_t g_pwm_buffer[IS31FL3741_DRIVER_COUNT][IS31FL3741_MAX_LEDS];
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bool g_pwm_buffer_update_required[IS31FL3741_DRIVER_COUNT] = {false};
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bool g_scaling_registers_update_required[IS31FL3741_DRIVER_COUNT] = {false};
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uint8_t g_scaling_registers[IS31FL3741_DRIVER_COUNT][IS31FL3741_MAX_LEDS];
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void is31fl3741_write_register(uint8_t addr, uint8_t reg, uint8_t data) {
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g_twi_transfer_buffer[0] = reg;
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g_twi_transfer_buffer[1] = data;
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#if IS31FL3741_I2C_PERSISTENCE > 0
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for (uint8_t i = 0; i < IS31FL3741_I2C_PERSISTENCE; i++) {
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if (i2c_transmit(addr << 1, g_twi_transfer_buffer, 2, IS31FL3741_I2C_TIMEOUT) == 0) break;
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}
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#else
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i2c_transmit(addr << 1, g_twi_transfer_buffer, 2, IS31FL3741_I2C_TIMEOUT);
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#endif
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}
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bool is31fl3741_write_pwm_buffer(uint8_t addr, uint8_t *pwm_buffer) {
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// Assume PG0 is already selected
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for (int i = 0; i < 342; i += 18) {
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if (i == 180) {
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// unlock the command register and select PG1
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER_WRITELOCK, 0xC5);
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER, IS31FL3741_PAGE_PWM1);
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}
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g_twi_transfer_buffer[0] = i % 180;
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memcpy(g_twi_transfer_buffer + 1, pwm_buffer + i, 18);
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#if IS31FL3741_I2C_PERSISTENCE > 0
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for (uint8_t i = 0; i < IS31FL3741_I2C_PERSISTENCE; i++) {
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if (i2c_transmit(addr << 1, g_twi_transfer_buffer, 19, IS31FL3741_I2C_TIMEOUT) != 0) {
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return false;
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}
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}
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#else
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if (i2c_transmit(addr << 1, g_twi_transfer_buffer, 19, IS31FL3741_I2C_TIMEOUT) != 0) {
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return false;
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}
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#endif
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}
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// transfer the left cause the total number is 351
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g_twi_transfer_buffer[0] = 162;
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memcpy(g_twi_transfer_buffer + 1, pwm_buffer + 342, 9);
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#if IS31FL3741_I2C_PERSISTENCE > 0
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for (uint8_t i = 0; i < IS31FL3741_I2C_PERSISTENCE; i++) {
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if (i2c_transmit(addr << 1, g_twi_transfer_buffer, 10, IS31FL3741_I2C_TIMEOUT) != 0) {
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return false;
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}
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}
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#else
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if (i2c_transmit(addr << 1, g_twi_transfer_buffer, 10, IS31FL3741_I2C_TIMEOUT) != 0) {
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return false;
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}
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#endif
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return true;
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}
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void is31fl3741_init(uint8_t addr) {
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// In order to avoid the LEDs being driven with garbage data
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// in the LED driver's PWM registers, shutdown is enabled last.
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// Set up the mode and other settings, clear the PWM registers,
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// then disable software shutdown.
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// Unlock the command register.
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// Unlock the command register.
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER_WRITELOCK, 0xC5);
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// Select PG4
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER, IS31FL3741_PAGE_FUNCTION);
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// Set to Normal operation
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is31fl3741_write_register(addr, IS31FL3741_REG_CONFIGURATION, IS31FL3741_CONFIGURATION);
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// Set Golbal Current Control Register
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is31fl3741_write_register(addr, IS31FL3741_REG_GLOBALCURRENT, IS31FL3741_GLOBALCURRENT);
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// Set Pull up & Down for SWx CSy
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is31fl3741_write_register(addr, IS31FL3741_REG_PULLDOWNUP, ((IS31FL3741_CSPULLUP << 4) | IS31FL3741_SWPULLUP));
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// Set PWM frequency
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is31fl3741_write_register(addr, IS31FL3741_REG_PWM_FREQUENCY, (IS31FL3741_PWM_FREQUENCY & 0b1111));
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// is31fl3741_update_led_scaling_registers(addr, 0xFF, 0xFF, 0xFF);
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// Wait 10ms to ensure the device has woken up.
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wait_ms(10);
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}
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void is31fl3741_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
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is31_led led;
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if (index >= 0 && index < RGB_MATRIX_LED_COUNT) {
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memcpy_P(&led, (&g_is31_leds[index]), sizeof(led));
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if (g_pwm_buffer[led.driver][led.r] == red && g_pwm_buffer[led.driver][led.g] == green && g_pwm_buffer[led.driver][led.b] == blue) {
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return;
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}
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g_pwm_buffer_update_required[led.driver] = true;
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g_pwm_buffer[led.driver][led.r] = red;
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g_pwm_buffer[led.driver][led.g] = green;
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g_pwm_buffer[led.driver][led.b] = blue;
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}
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}
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void is31fl3741_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
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for (int i = 0; i < RGB_MATRIX_LED_COUNT; i++) {
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is31fl3741_set_color(i, red, green, blue);
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}
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}
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void is31fl3741_set_led_control_register(uint8_t index, bool red, bool green, bool blue) {
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is31_led led;
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memcpy_P(&led, (&g_is31_leds[index]), sizeof(led));
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if (red) {
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g_scaling_registers[led.driver][led.r] = 0xFF;
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} else {
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g_scaling_registers[led.driver][led.r] = 0x00;
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}
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if (green) {
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g_scaling_registers[led.driver][led.g] = 0xFF;
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} else {
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g_scaling_registers[led.driver][led.g] = 0x00;
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}
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if (blue) {
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g_scaling_registers[led.driver][led.b] = 0xFF;
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} else {
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g_scaling_registers[led.driver][led.b] = 0x00;
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}
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g_scaling_registers_update_required[led.driver] = true;
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}
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void is31fl3741_update_pwm_buffers(uint8_t addr, uint8_t index) {
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if (g_pwm_buffer_update_required[index]) {
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// unlock the command register and select PG2
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER_WRITELOCK, 0xC5);
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER, IS31FL3741_PAGE_PWM0);
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is31fl3741_write_pwm_buffer(addr, g_pwm_buffer[index]);
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}
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g_pwm_buffer_update_required[index] = false;
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}
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void is31fl3741_set_pwm_buffer(const is31_led *pled, uint8_t red, uint8_t green, uint8_t blue) {
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g_pwm_buffer[pled->driver][pled->r] = red;
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g_pwm_buffer[pled->driver][pled->g] = green;
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g_pwm_buffer[pled->driver][pled->b] = blue;
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g_pwm_buffer_update_required[pled->driver] = true;
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}
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void is31fl3741_update_led_control_registers(uint8_t addr, uint8_t index) {
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if (g_scaling_registers_update_required[index]) {
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// unlock the command register and select PG2
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER_WRITELOCK, 0xC5);
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER, IS31FL3741_PAGE_SCALING_0);
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// CS1_SW1 to CS30_SW6 are on PG2
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for (int i = CS1_SW1; i <= CS30_SW6; ++i) {
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is31fl3741_write_register(addr, i, g_scaling_registers[index][i]);
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}
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// unlock the command register and select PG3
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER_WRITELOCK, 0xC5);
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is31fl3741_write_register(addr, IS31FL3741_COMMANDREGISTER, IS31FL3741_PAGE_SCALING_1);
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// CS1_SW7 to CS39_SW9 are on PG3
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for (int i = CS1_SW7; i <= CS39_SW9; ++i) {
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is31fl3741_write_register(addr, i - CS1_SW7, g_scaling_registers[index][i]);
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}
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g_scaling_registers_update_required[index] = false;
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}
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}
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void is31fl3741_set_scaling_registers(const is31_led *pled, uint8_t red, uint8_t green, uint8_t blue) {
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g_scaling_registers[pled->driver][pled->r] = red;
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g_scaling_registers[pled->driver][pled->g] = green;
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g_scaling_registers[pled->driver][pled->b] = blue;
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g_scaling_registers_update_required[pled->driver] = true;
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}
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