forked from mirrors/qmk_firmware
423 lines
18 KiB
PHP
423 lines
18 KiB
PHP
/* Name: usbdrvasm15.inc
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* Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
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* Author: contributed by V. Bosch
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* Creation Date: 2007-08-06
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* Tabsize: 4
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* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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* License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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* Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $
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*/
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/* Do not link this file! Link usbdrvasm.S instead, which includes the
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* appropriate implementation!
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*/
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/*
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General Description:
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This file is the 15 MHz version of the asssembler part of the USB driver. It
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requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
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oscillator).
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See usbdrv.h for a description of the entire driver.
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Since almost all of this code is timing critical, don't change unless you
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really know what you are doing! Many parts require not only a maximum number
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of CPU cycles, but even an exact number of cycles!
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*/
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;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
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;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
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; Numbers in brackets are clocks counted from center of last sync bit
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; when instruction starts
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;----------------------------------------------------------------------------
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; order of registers pushed:
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; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
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;----------------------------------------------------------------------------
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USB_INTR_VECTOR:
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push YL ;2 push only what is necessary to sync with edge ASAP
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in YL, SREG ;1
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push YL ;2
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;----------------------------------------------------------------------------
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; Synchronize with sync pattern:
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;
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; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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; sync up with J to K edge during sync pattern -- use fastest possible loops
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;The first part waits at most 1 bit long since we must be in sync pattern.
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;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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;waitForJ, ensure that this prerequisite is met.
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waitForJ:
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inc YL
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sbis USBIN, USBMINUS
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brne waitForJ ; just make sure we have ANY timeout
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;-------------------------------------------------------------------------------
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; The following code results in a sampling window of < 1/4 bit
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; which meets the spec.
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;-------------------------------------------------------------------------------
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waitForK: ;-
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sbis USBIN, USBMINUS ;1 [00] <-- sample
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rjmp foundK ;2 [01]
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sbis USBIN, USBMINUS ; <-- sample
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rjmp foundK
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sbis USBIN, USBMINUS ; <-- sample
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rjmp foundK
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sbis USBIN, USBMINUS ; <-- sample
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rjmp foundK
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sbis USBIN, USBMINUS ; <-- sample
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rjmp foundK
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sbis USBIN, USBMINUS ; <-- sample
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rjmp foundK
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#if USB_COUNT_SOF
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lds YL, usbSofCount
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inc YL
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sts usbSofCount, YL
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#endif /* USB_COUNT_SOF */
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#ifdef USB_SOF_HOOK
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USB_SOF_HOOK
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#endif
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rjmp sofError
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;------------------------------------------------------------------------------
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; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
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; center sampling]
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; we have 1 bit time for setup purposes, then sample again.
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; Numbers in brackets are cycles from center of first sync (double K)
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; bit after the instruction
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;------------------------------------------------------------------------------
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foundK: ;- [02]
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lds YL, usbInputBufOffset;2 [03+04] tx loop
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push YH ;2 [05+06]
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clr YH ;1 [07]
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subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
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sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
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push shift ;2 [10+11]
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ser shift ;1 [12]
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sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
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rjmp haveTwoBitsK ;2 [00] [14]
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pop shift ;2 [15+16] undo the push from before
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pop YH ;2 [17+18] undo the push from before
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rjmp waitForK ;2 [19+20] this was not the end of sync, retry
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; The entire loop from waitForK until rjmp waitForK above must not exceed two
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; bit times (= 20 cycles).
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;----------------------------------------------------------------------------
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; push more registers and initialize values while we sample the first bits:
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;----------------------------------------------------------------------------
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haveTwoBitsK: ;- [01]
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push x1 ;2 [02+03]
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push x2 ;2 [04+05]
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push x3 ;2 [06+07]
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push bitcnt ;2 [08+09]
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in x1, USBIN ;1 [00] [10] <-- sample bit 0
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bst x1, USBMINUS ;1 [01]
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bld shift, 0 ;1 [02]
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push cnt ;2 [03+04]
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ldi cnt, USB_BUFSIZE ;1 [05]
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push x4 ;2 [06+07] tx loop
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rjmp rxLoop ;2 [08]
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;----------------------------------------------------------------------------
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; Receiver loop (numbers in brackets are cycles within byte after instr)
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;----------------------------------------------------------------------------
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unstuff0: ;- [07] (branch taken)
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andi x3, ~0x01 ;1 [08]
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mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
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in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
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andi x2, USBMASK ;1 [01]
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breq se0Hop ;1 [02] SE0 check for bit 1
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ori shift, 0x01 ;1 [03] 0b00000001
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nop ;1 [04]
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rjmp didUnstuff0 ;2 [05]
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;-----------------------------------------------------
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unstuff1: ;- [05] (branch taken)
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mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
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andi x3, ~0x02 ;1 [07]
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ori shift, 0x02 ;1 [08] 0b00000010
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nop ;1 [09]
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in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
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andi x1, USBMASK ;1 [01]
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breq se0Hop ;1 [02] SE0 check for bit 2
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rjmp didUnstuff1 ;2 [03]
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;-----------------------------------------------------
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unstuff2: ;- [05] (branch taken)
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andi x3, ~0x04 ;1 [06]
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ori shift, 0x04 ;1 [07] 0b00000100
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mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
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nop ;1 [09]
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in x2, USBIN ;1 [00] [10] <-- sample bit 3
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andi x2, USBMASK ;1 [01]
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breq se0Hop ;1 [02] SE0 check for bit 3
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rjmp didUnstuff2 ;2 [03]
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;-----------------------------------------------------
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unstuff3: ;- [00] [10] (branch taken)
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in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
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andi x2, USBMASK ;1 [02]
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breq se0Hop ;1 [03] SE0 check for stuffed bit 3
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andi x3, ~0x08 ;1 [04]
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ori shift, 0x08 ;1 [05] 0b00001000
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rjmp didUnstuff3 ;2 [06]
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;----------------------------------------------------------------------------
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; extra jobs done during bit interval:
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;
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; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
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; overflow check, jump to the head of rxLoop
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; bit 1: SE0 check
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; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
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; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
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; bit 4: SE0 check, none
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; bit 5: SE0 check, none
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; bit 6: SE0 check, none
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; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
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;----------------------------------------------------------------------------
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rxLoop: ;- [09]
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in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
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andi x2, USBMASK ;1 [01]
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brne SkipSe0Hop ;1 [02]
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se0Hop: ;- [02]
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rjmp se0 ;2 [03] SE0 check for bit 1
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SkipSe0Hop: ;- [03]
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ser x3 ;1 [04]
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andi shift, 0xf9 ;1 [05] 0b11111001
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breq unstuff0 ;1 [06]
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didUnstuff0: ;- [06]
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eor x1, x2 ;1 [07]
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bst x1, USBMINUS ;1 [08]
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bld shift, 1 ;1 [09]
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in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
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andi x1, USBMASK ;1 [01]
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breq se0Hop ;1 [02] SE0 check for bit 2
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andi shift, 0xf3 ;1 [03] 0b11110011
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breq unstuff1 ;1 [04] do remaining work for bit 1
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didUnstuff1: ;- [04]
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eor x2, x1 ;1 [05]
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bst x2, USBMINUS ;1 [06]
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bld shift, 2 ;1 [07]
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nop2 ;2 [08+09]
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in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
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andi x2, USBMASK ;1 [01]
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breq se0Hop ;1 [02] SE0 check for bit 3
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andi shift, 0xe7 ;1 [03] 0b11100111
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breq unstuff2 ;1 [04]
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didUnstuff2: ;- [04]
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eor x1, x2 ;1 [05]
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bst x1, USBMINUS ;1 [06]
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bld shift, 3 ;1 [07]
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didUnstuff3: ;- [07]
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andi shift, 0xcf ;1 [08] 0b11001111
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breq unstuff3 ;1 [09]
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in x1, USBIN ;1 [00] [10] <-- sample bit 4
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andi x1, USBMASK ;1 [01]
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breq se0Hop ;1 [02] SE0 check for bit 4
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eor x2, x1 ;1 [03]
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bst x2, USBMINUS ;1 [04]
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bld shift, 4 ;1 [05]
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didUnstuff4: ;- [05]
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andi shift, 0x9f ;1 [06] 0b10011111
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breq unstuff4 ;1 [07]
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nop2 ;2 [08+09]
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in x2, USBIN ;1 [00] [10] <-- sample bit 5
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andi x2, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for bit 5
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eor x1, x2 ;1 [03]
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bst x1, USBMINUS ;1 [04]
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bld shift, 5 ;1 [05]
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didUnstuff5: ;- [05]
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andi shift, 0x3f ;1 [06] 0b00111111
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breq unstuff5 ;1 [07]
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nop2 ;2 [08+09]
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in x1, USBIN ;1 [00] [10] <-- sample bit 6
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andi x1, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for bit 6
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eor x2, x1 ;1 [03]
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bst x2, USBMINUS ;1 [04]
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bld shift, 6 ;1 [05]
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didUnstuff6: ;- [05]
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cpi shift, 0x02 ;1 [06] 0b00000010
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brlo unstuff6 ;1 [07]
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nop2 ;2 [08+09]
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in x2, USBIN ;1 [00] [10] <-- sample bit 7
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andi x2, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for bit 7
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eor x1, x2 ;1 [03]
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bst x1, USBMINUS ;1 [04]
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bld shift, 7 ;1 [05]
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didUnstuff7: ;- [05]
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cpi shift, 0x04 ;1 [06] 0b00000100
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brlo unstuff7 ;1 [07]
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eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
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nop ;1 [09]
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in x1, USBIN ;1 [00] [10] <-- sample bit 0
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st y+, x3 ;2 [01+02] store data
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eor x2, x1 ;1 [03]
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bst x2, USBMINUS ;1 [04]
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bld shift, 0 ;1 [05]
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subi cnt, 1 ;1 [06]
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brcs overflow ;1 [07]
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rjmp rxLoop ;2 [08]
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;-----------------------------------------------------
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unstuff4: ;- [08]
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andi x3, ~0x10 ;1 [09]
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in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
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andi x1, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for stuffed bit 4
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ori shift, 0x10 ;1 [03]
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rjmp didUnstuff4 ;2 [04]
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;-----------------------------------------------------
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unstuff5: ;- [08]
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ori shift, 0x20 ;1 [09]
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in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
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andi x2, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for stuffed bit 5
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andi x3, ~0x20 ;1 [03]
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rjmp didUnstuff5 ;2 [04]
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;-----------------------------------------------------
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unstuff6: ;- [08]
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andi x3, ~0x40 ;1 [09]
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in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
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andi x1, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for stuffed bit 6
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ori shift, 0x40 ;1 [03]
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rjmp didUnstuff6 ;2 [04]
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;-----------------------------------------------------
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unstuff7: ;- [08]
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andi x3, ~0x80 ;1 [09]
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in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
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andi x2, USBMASK ;1 [01]
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breq se0 ;1 [02] SE0 check for stuffed bit 7
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ori shift, 0x80 ;1 [03]
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rjmp didUnstuff7 ;2 [04]
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macro POP_STANDARD ; 16 cycles
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pop x4
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pop cnt
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pop bitcnt
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pop x3
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pop x2
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pop x1
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pop shift
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pop YH
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endm
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macro POP_RETI ; 5 cycles
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pop YL
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out SREG, YL
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pop YL
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endm
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#include "asmcommon.inc"
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;---------------------------------------------------------------------------
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; USB spec says:
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; idle = J
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; J = (D+ = 0), (D- = 1)
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; K = (D+ = 1), (D- = 0)
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; Spec allows 7.5 bit times from EOP to SOP for replies
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;---------------------------------------------------------------------------
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bitstuffN: ;- [04]
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eor x1, x4 ;1 [05]
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clr x2 ;1 [06]
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nop ;1 [07]
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rjmp didStuffN ;1 [08]
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;---------------------------------------------------------------------------
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bitstuff6: ;- [04]
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eor x1, x4 ;1 [05]
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clr x2 ;1 [06]
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rjmp didStuff6 ;1 [07]
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;---------------------------------------------------------------------------
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bitstuff7: ;- [02]
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eor x1, x4 ;1 [03]
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clr x2 ;1 [06]
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nop ;1 [05]
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rjmp didStuff7 ;1 [06]
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;---------------------------------------------------------------------------
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sendNakAndReti: ;- [-19]
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ldi x3, USBPID_NAK ;1 [-18]
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rjmp sendX3AndReti ;1 [-17]
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;---------------------------------------------------------------------------
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sendAckAndReti: ;- [-17]
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ldi cnt, USBPID_ACK ;1 [-16]
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sendCntAndReti: ;- [-16]
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mov x3, cnt ;1 [-15]
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sendX3AndReti: ;- [-15]
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ldi YL, 20 ;1 [-14] x3==r20 address is 20
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ldi YH, 0 ;1 [-13]
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ldi cnt, 2 ;1 [-12]
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; rjmp usbSendAndReti fallthrough
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;---------------------------------------------------------------------------
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;usbSend:
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;pointer to data in 'Y'
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;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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;uses: x1...x4, btcnt, shift, cnt, Y
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;Numbers in brackets are time since first bit of sync pattern is sent
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;We need not to match the transfer rate exactly because the spec demands
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;only 1.5% precision anyway.
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usbSendAndReti: ;- [-13] 13 cycles until SOP
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in x2, USBDDR ;1 [-12]
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ori x2, USBMASK ;1 [-11]
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sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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in x1, USBOUT ;1 [-08] port mirror for tx loop
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out USBDDR, x2 ;1 [-07] <- acquire bus
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; need not init x2 (bitstuff history) because sync starts with 0
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ldi x4, USBMASK ;1 [-06] exor mask
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ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
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ldi bitcnt, 6 ;1 [-04]
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txBitLoop: ;- [-04] [06]
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sbrs shift, 0 ;1 [-03] [07]
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eor x1, x4 ;1 [-02] [08]
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ror shift ;1 [-01] [09]
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didStuffN: ;- [09]
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out USBOUT, x1 ;1 [00] [10] <-- out N
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ror x2 ;1 [01]
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cpi x2, 0xfc ;1 [02]
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brcc bitstuffN ;1 [03]
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dec bitcnt ;1 [04]
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brne txBitLoop ;1 [05]
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sbrs shift, 0 ;1 [06]
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eor x1, x4 ;1 [07]
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ror shift ;1 [08]
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didStuff6: ;- [08]
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nop ;1 [09]
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out USBOUT, x1 ;1 [00] [10] <-- out 6
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ror x2 ;1 [01]
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cpi x2, 0xfc ;1 [02]
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brcc bitstuff6 ;1 [03]
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sbrs shift, 0 ;1 [04]
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eor x1, x4 ;1 [05]
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ror shift ;1 [06]
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ror x2 ;1 [07]
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didStuff7: ;- [07]
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ldi bitcnt, 6 ;1 [08]
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cpi x2, 0xfc ;1 [09]
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out USBOUT, x1 ;1 [00] [10] <-- out 7
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brcc bitstuff7 ;1 [01]
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ld shift, y+ ;2 [02+03]
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dec cnt ;1 [04]
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brne txBitLoop ;1 [05]
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makeSE0:
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cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
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lds x2, usbNewDeviceAddr;2 [07+08]
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lsl x2 ;1 [09] we compare with left shifted address
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;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
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;set address only after data packet was sent, not after handshake
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out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
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subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
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sbci YH, 0 ;1 [02]
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breq skipAddrAssign ;1 [03]
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sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
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;----------------------------------------------------------------------------
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;end of usbDeviceAddress transfer
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skipAddrAssign: ;- [03/04]
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ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
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USB_STORE_PENDING(x2) ;1 [06]
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ori x1, USBIDLE ;1 [07]
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in x2, USBDDR ;1 [08]
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cbr x2, USBMASK ;1 [09] set both pins to input
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mov x3, x1 ;1 [10]
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cbr x3, USBMASK ;1 [11] configure no pullup on both pins
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ldi x4, 3 ;1 [12]
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se0Delay: ;- [12] [15]
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dec x4 ;1 [13] [16]
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brne se0Delay ;1 [14] [17]
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nop2 ;2 [18+19]
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out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
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out USBDDR, x2 ;1 [21] <--release bus now
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out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
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rjmp doReturn ;1 [23]
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;---------------------------------------------------------------------------
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