forked from mirrors/qmk_firmware
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4) Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers (that macro should not have been there, because ADCv3 has CFGR instead of CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS if it is defined (that name is used for ADCv3 and ADCv4). * Update ADC docs to match the actually used resolution ADC driver for ChibiOS actually uses the 10-bit resolution by default (probably to match AVR); fix the documentation accordingly. Also add both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names differ according to the ADC implementation in the particular MCU). * Fix pinToMux() for B12 and B13 on STM32F3xx Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and B13 pins were wrong. * Add support for all possible analog pins on STM32F1xx Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx (they are the same at least for STM32F103x8 and larger F103 devices, and also F102, F105, F107 families). Actually tested on STM32F103C8T6 (therefore pins C0...C5 were not tested). Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages, cannot be supported at the moment, because those pins are connected only to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1. * Add support for all possible analog pins on STM32F4xx Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are apparently the same for all F4xx devices, except some smaller devices may not have ADC3. Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested. Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices which don't have ADC3 also don't have the GPIOF port, therefore the code which refers to Fx pins does not compile. * Fix STM32F3xx ADC mux table in documentation The ADC driver documentation had some errors in the mux table for STM32F3xx. Fix this table to match the datasheet and the actual code (mux settings for B12 and B13 were also tested on a real STM32F303CCT6 chip). * Add STM32F1xx ADC pins to the documentation * Add STM32F4xx ADC pins to the documentation
This commit is contained in:
Sergey Vlasov
GitHub
parent
f12aea5dfb
commit
65c9752762
2 changed files with 131 additions and 80 deletions
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@ -47,73 +47,79 @@ Note that some of these pins are doubled-up on ADCs with the same channel. This
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Also note that the F0 and F3 use different numbering schemes. The F0 has a single ADC and the channels are 0-indexed, whereas the F3 has 4 ADCs and the channels are 1-indexed. This is because the F0 uses the `ADCv1` implementation of the ADC, whereas the F3 uses the `ADCv3` implementation.
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|ADC|Channel|STM32F0xx|STM32F3xx|
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|---|-------|---------|---------|
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|1 |0 |`A0` | |
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|1 |1 |`A1` |`A0` |
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|1 |2 |`A2` |`A1` |
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|1 |3 |`A3` |`A2` |
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|1 |4 |`A4` |`A3` |
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|1 |5 |`A5` |`F4` |
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|1 |6 |`A6` |`C0` |
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|1 |7 |`A7` |`C1` |
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|1 |8 |`B0` |`C2` |
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|1 |9 |`B1` |`C3` |
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|1 |10 |`C0` |`F2` |
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|1 |11 |`C1` | |
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|1 |12 |`C2` | |
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|1 |13 |`C3` | |
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|1 |14 |`C4` | |
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|1 |15 |`C5` | |
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|1 |16 | | |
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|2 |1 | |`A4` |
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|2 |2 | |`A5` |
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|2 |3 | |`A6` |
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|2 |4 | |`A7` |
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|2 |5 | |`C4` |
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|2 |6 | |`C0` |
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|2 |7 | |`C1` |
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|2 |8 | |`C2` |
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|2 |9 | |`C3` |
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|2 |10 | |`F2` |
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|2 |11 | |`C5` |
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|2 |12 | |`B2` |
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|2 |13 | | |
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|2 |14 | | |
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|2 |15 | | |
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|2 |16 | | |
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|3 |1 | |`B1` |
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|3 |2 | |`E9` |
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|3 |3 | |`E13` |
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|3 |4 | | |
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|3 |5 | | |
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|3 |6 | |`E8` |
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|3 |7 | |`D10` |
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|3 |8 | |`D11` |
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|3 |9 | |`D12` |
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|3 |10 | |`D13` |
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|3 |11 | |`D14` |
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|3 |12 | |`B0` |
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|3 |13 | |`E7` |
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|3 |14 | |`E10` |
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|3 |15 | |`E11` |
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|3 |16 | |`E12` |
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|4 |1 | |`E14` |
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|4 |2 | |`B12` |
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|4 |3 | |`B13` |
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|4 |4 | |`B14` |
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|4 |5 | |`B15` |
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|4 |6 | |`E8` |
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|4 |7 | |`D10` |
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|4 |8 | |`D11` |
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|4 |9 | |`D12` |
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|4 |10 | |`D13` |
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|4 |11 | |`D14` |
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|4 |12 | |`D8` |
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|4 |13 | |`D9` |
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|4 |14 | | |
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|4 |15 | | |
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|4 |16 | | |
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|ADC|Channel|STM32F0xx|STM32F1xx|STM32F3xx|STM32F4xx|
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|---|-------|---------|---------|---------|---------|
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|1 |0 |`A0` |`A0` | |`A0` |
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|1 |1 |`A1` |`A1` |`A0` |`A1` |
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|1 |2 |`A2` |`A2` |`A1` |`A2` |
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|1 |3 |`A3` |`A3` |`A2` |`A3` |
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|1 |4 |`A4` |`A4` |`A3` |`A4` |
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|1 |5 |`A5` |`A5` |`F4` |`A5` |
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|1 |6 |`A6` |`A6` |`C0` |`A6` |
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|1 |7 |`A7` |`A7` |`C1` |`A7` |
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|1 |8 |`B0` |`B0` |`C2` |`B0` |
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|1 |9 |`B1` |`B1` |`C3` |`B1` |
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|1 |10 |`C0` |`C0` |`F2` |`C0` |
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|1 |11 |`C1` |`C1` | |`C1` |
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|1 |12 |`C2` |`C2` | |`C2` |
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|1 |13 |`C3` |`C3` | |`C3` |
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|1 |14 |`C4` |`C4` | |`C4` |
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|1 |15 |`C5` |`C5` | |`C5` |
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|1 |16 | | | | |
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|2 |0 | |`A0`¹ | |`A0`² |
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|2 |1 | |`A1`¹ |`A4` |`A1`² |
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|2 |2 | |`A2`¹ |`A5` |`A2`² |
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|2 |3 | |`A3`¹ |`A6` |`A3`² |
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|2 |4 | |`A4`¹ |`A7` |`A4`² |
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|2 |5 | |`A5`¹ |`C4` |`A5`² |
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|2 |6 | |`A6`¹ |`C0` |`A6`² |
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|2 |7 | |`A7`¹ |`C1` |`A7`² |
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|2 |8 | |`B0`¹ |`C2` |`B0`² |
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|2 |9 | |`B1`¹ |`C3` |`B1`² |
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|2 |10 | |`C0`¹ |`F2` |`C0`² |
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|2 |11 | |`C1`¹ |`C5` |`C1`² |
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|2 |12 | |`C2`¹ |`B2` |`C2`² |
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|2 |13 | |`C3`¹ | |`C3`² |
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|2 |14 | |`C4`¹ | |`C4`² |
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|2 |15 | |`C5`¹ | |`C5`² |
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|2 |16 | | | | |
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|3 |0 | |`A0`¹ | |`A0`² |
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|3 |1 | |`A1`¹ |`B1` |`A1`² |
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|3 |2 | |`A2`¹ |`E9` |`A2`² |
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|3 |3 | |`A3`¹ |`E13` |`A3`² |
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|3 |4 | |`F6`¹ | |`F6`² |
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|3 |5 | |`F7`¹ |`B13` |`F7`² |
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|3 |6 | |`F8`¹ |`E8` |`F8`² |
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|3 |7 | |`F9`¹ |`D10` |`F9`² |
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|3 |8 | |`F10`¹ |`D11` |`F10`² |
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|3 |9 | | |`D12` |`F3`² |
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|3 |10 | |`C0`¹ |`D13` |`C0`² |
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|3 |11 | |`C1`¹ |`D14` |`C1`² |
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|3 |12 | |`C2`¹ |`B0` |`C2`² |
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|3 |13 | |`C3`¹ |`E7` |`C3`² |
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|3 |14 | | |`E10` |`F4`² |
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|3 |15 | | |`E11` |`F5`² |
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|3 |16 | | |`E12` | |
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|4 |1 | | |`E14` | |
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|4 |2 | | |`E15` | |
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|4 |3 | | |`B12` | |
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|4 |4 | | |`B14` | |
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|4 |5 | | |`B15` | |
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|4 |6 | | |`E8` | |
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|4 |7 | | |`D10` | |
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|4 |8 | | |`D11` | |
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|4 |9 | | |`D12` | |
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|4 |10 | | |`D13` | |
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|4 |11 | | |`D14` | |
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|4 |12 | | |`D8` | |
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|4 |13 | | |`D9` | |
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|4 |14 | | | | |
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|4 |15 | | | | |
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|4 |16 | | | | |
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<sup>¹ As of ChibiOS 20.3.4, the ADC driver for STM32F1xx devices supports only ADC1, therefore any configurations involving ADC2 or ADC3 cannot actually be used. In particular, pins `F6`…`F10`, which are present at least on some STM32F103x[C-G] devices, cannot be used as ADC inputs because of this driver limitation.</sup>
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<sup>² Not all STM32F4xx devices have ADC2 and/or ADC3, therefore some configurations shown in this table may be unavailable; in particular, pins `F4`…`F10` cannot be used as ADC inputs on devices which do not have ADC3. Check the device datasheet to confirm which pin functions are supported.</sup>
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## Functions
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@ -141,10 +147,10 @@ Also note that the F0 and F3 use different numbering schemes. The F0 has a singl
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The ARM implementation of the ADC has a few additional options that you can override in your own keyboards and keymaps to change how it operates. Please consult the corresponding `hal_adc_lld.h` in ChibiOS for your specific microcontroller for further documentation on your available options.
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|`#define` |Type |Default |Description |
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|---------------------|------|---------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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|`ADC_CIRCULAR_BUFFER`|`bool`|`false` |If `true`, then the implementation will use a circular buffer. |
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|`ADC_NUM_CHANNELS` |`int` |`1` |Sets the number of channels that will be scanned as part of an ADC operation. The current implementation only supports `1`. |
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|`ADC_BUFFER_DEPTH` |`int` |`2` |Sets the depth of each result. Since we are only getting a 12-bit result by default, we set this to 2 bytes so we can contain our one value. This could be set to 1 if you opt for an 8-bit or lower result.|
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|`ADC_SAMPLING_RATE` |`int` |`ADC_SMPR_SMP_1P5` |Sets the sampling rate of the ADC. By default, it is set to the fastest setting. |
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|`ADC_RESOLUTION` |`int` |`ADC_CFGR1_RES_12BIT`|The resolution of your result. We choose 12 bit by default, but you can opt for 12, 10, 8, or 6 bit. |
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|`#define` |Type |Default |Description |
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|---------------------|------|----------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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|`ADC_CIRCULAR_BUFFER`|`bool`|`false` |If `true`, then the implementation will use a circular buffer. |
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|`ADC_NUM_CHANNELS` |`int` |`1` |Sets the number of channels that will be scanned as part of an ADC operation. The current implementation only supports `1`. |
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|`ADC_BUFFER_DEPTH` |`int` |`2` |Sets the depth of each result. Since we are only getting a 10-bit result by default, we set this to 2 bytes so we can contain our one value. This could be set to 1 if you opt for an 8-bit or lower result.|
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|`ADC_SAMPLING_RATE` |`int` |`ADC_SMPR_SMP_1P5` |Sets the sampling rate of the ADC. By default, it is set to the fastest setting. |
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|`ADC_RESOLUTION` |`int` |`ADC_CFGR1_RES_10BIT` or `ADC_CFGR_RES_10BITS`|The resolution of your result. We choose 10 bit by default, but you can opt for 12, 10, 8, or 6 bit. Different MCUs use slightly different names for the resolution constants. |
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@ -101,7 +101,11 @@
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// Options are 12, 10, 8, and 6 bit.
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#ifndef ADC_RESOLUTION
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# define ADC_RESOLUTION ADC_CFGR1_RES_10BIT
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# ifdef ADC_CFGR_RES_10BITS // ADCv3, ADCv4
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# define ADC_RESOLUTION ADC_CFGR_RES_10BITS
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# else // ADCv1, ADCv5, or the bodge for ADCv2 above
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# define ADC_RESOLUTION ADC_CFGR1_RES_10BIT
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# endif
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#endif
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static ADCConfig adcCfg = {};
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@ -161,8 +165,8 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
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case B0: return TO_MUX( ADC_CHANNEL_IN12, 2 );
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case B1: return TO_MUX( ADC_CHANNEL_IN1, 2 );
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case B2: return TO_MUX( ADC_CHANNEL_IN12, 1 );
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case B12: return TO_MUX( ADC_CHANNEL_IN2, 3 );
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case B13: return TO_MUX( ADC_CHANNEL_IN3, 3 );
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case B12: return TO_MUX( ADC_CHANNEL_IN3, 3 );
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case B13: return TO_MUX( ADC_CHANNEL_IN5, 2 );
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case B14: return TO_MUX( ADC_CHANNEL_IN4, 3 );
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case B15: return TO_MUX( ADC_CHANNEL_IN5, 3 );
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case C0: return TO_MUX( ADC_CHANNEL_IN6, 0 ); // Can also be ADC2
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@ -189,11 +193,52 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
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case E15: return TO_MUX( ADC_CHANNEL_IN2, 3 );
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case F2: return TO_MUX( ADC_CHANNEL_IN10, 0 ); // Can also be ADC2
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case F4: return TO_MUX( ADC_CHANNEL_IN5, 0 );
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#elif defined(STM32F4XX) // TODO: add all pins
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#elif defined(STM32F4XX)
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case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
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//case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
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#elif defined(STM32F1XX) // TODO: add all pins
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case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
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case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
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case A3: return TO_MUX( ADC_CHANNEL_IN3, 0 );
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case A4: return TO_MUX( ADC_CHANNEL_IN4, 0 );
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case A5: return TO_MUX( ADC_CHANNEL_IN5, 0 );
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case A6: return TO_MUX( ADC_CHANNEL_IN6, 0 );
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case A7: return TO_MUX( ADC_CHANNEL_IN7, 0 );
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case B0: return TO_MUX( ADC_CHANNEL_IN8, 0 );
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case B1: return TO_MUX( ADC_CHANNEL_IN9, 0 );
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case C0: return TO_MUX( ADC_CHANNEL_IN10, 0 );
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case C1: return TO_MUX( ADC_CHANNEL_IN11, 0 );
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case C2: return TO_MUX( ADC_CHANNEL_IN12, 0 );
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case C3: return TO_MUX( ADC_CHANNEL_IN13, 0 );
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case C4: return TO_MUX( ADC_CHANNEL_IN14, 0 );
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case C5: return TO_MUX( ADC_CHANNEL_IN15, 0 );
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# if STM32_ADC_USE_ADC3
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case F3: return TO_MUX( ADC_CHANNEL_IN9, 2 );
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case F4: return TO_MUX( ADC_CHANNEL_IN14, 2 );
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case F5: return TO_MUX( ADC_CHANNEL_IN15, 2 );
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case F6: return TO_MUX( ADC_CHANNEL_IN4, 2 );
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case F7: return TO_MUX( ADC_CHANNEL_IN5, 2 );
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case F8: return TO_MUX( ADC_CHANNEL_IN6, 2 );
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case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
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case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
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# endif
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#elif defined(STM32F1XX)
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case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
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case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
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case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
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case A3: return TO_MUX( ADC_CHANNEL_IN3, 0 );
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case A4: return TO_MUX( ADC_CHANNEL_IN4, 0 );
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case A5: return TO_MUX( ADC_CHANNEL_IN5, 0 );
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case A6: return TO_MUX( ADC_CHANNEL_IN6, 0 );
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case A7: return TO_MUX( ADC_CHANNEL_IN7, 0 );
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case B0: return TO_MUX( ADC_CHANNEL_IN8, 0 );
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case B1: return TO_MUX( ADC_CHANNEL_IN9, 0 );
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case C0: return TO_MUX( ADC_CHANNEL_IN10, 0 );
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case C1: return TO_MUX( ADC_CHANNEL_IN11, 0 );
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case C2: return TO_MUX( ADC_CHANNEL_IN12, 0 );
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case C3: return TO_MUX( ADC_CHANNEL_IN13, 0 );
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case C4: return TO_MUX( ADC_CHANNEL_IN14, 0 );
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case C5: return TO_MUX( ADC_CHANNEL_IN15, 0 );
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// STM32F103x[C-G] in 144-pin packages also have analog inputs on F6...F10, but they are on ADC3, and the
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// ChibiOS ADC driver for STM32F1xx currently supports only ADC1, therefore these pins are not usable.
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#endif
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}
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