add riscv
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parent
6d39c62f2a
commit
9b7255c188
3 changed files with 19 additions and 10 deletions
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@ -10,6 +10,7 @@
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localSystems = rec {
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localSystems = rec {
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x86_64-linux.system = "x86_64-linux";
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x86_64-linux.system = "x86_64-linux";
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aarch64-linux.system = "aarch64-linux";
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aarch64-linux.system = "aarch64-linux";
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riscv64-linux.system = "riscv64-linux";
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default.system = system;
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default.system = system;
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skylake =
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skylake =
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x86_64-linux
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x86_64-linux
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@ -36,6 +37,11 @@
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gcc.arch = "znver2";
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gcc.arch = "znver2";
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gcc.tune = "znver2";
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gcc.tune = "znver2";
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};
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};
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rv64_zba_zbb =
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riscv64-linux
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// {
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gcc.arch = "rv64_zba_zbb";
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};
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};
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};
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pkgs-unpatched = import nixpkgs-unpatched' {
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pkgs-unpatched = import nixpkgs-unpatched' {
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inherit system;
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inherit system;
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@ -1,4 +1,4 @@
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{nixpkgs}: let
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let
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buildFor = system:
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buildFor = system:
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import ../. {
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import ../. {
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inherit nixpkgs system;
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inherit nixpkgs system;
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@ -7,4 +7,5 @@
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in {
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in {
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x86_64-linux = (buildFor "x86_64-linux").nixpkgs;
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x86_64-linux = (buildFor "x86_64-linux").nixpkgs;
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aarch64-linux = (buildFor "aarch64-linux").nixpkgs;
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aarch64-linux = (buildFor "aarch64-linux").nixpkgs;
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riscv64-linux = (buildFor "riscv64-linux").nixpkgs;
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}
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}
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@ -1,8 +1,8 @@
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diff --git a/lib/systems/architectures.nix b/lib/systems/architectures.nix
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diff --git a/lib/systems/architectures.nix b/lib/systems/architectures.nix
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index 94127fa9..5253e4bb 100644
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index 57b9184ca60..37d12ac687f 100644
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--- a/lib/systems/architectures.nix
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--- a/lib/systems/architectures.nix
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+++ b/lib/systems/architectures.nix
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+++ b/lib/systems/architectures.nix
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@@ -32,9 +32,24 @@ rec {
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@@ -32,9 +32,25 @@ rec {
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armv5te = [ ];
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armv5te = [ ];
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armv6 = [ ];
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armv6 = [ ];
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armv7-a = [ ];
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armv7-a = [ ];
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@ -22,13 +22,14 @@ index 94127fa9..5253e4bb 100644
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+ "armv9.3-a" = [ "mops" ] ++ features."armv9.2-a";
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+ "armv9.3-a" = [ "mops" ] ++ features."armv9.2-a";
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mips32 = [ ];
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mips32 = [ ];
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loongson2f = [ ];
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loongson2f = [ ];
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+ riscv64-g = [ "multiply" "atomic" "float" "double" "csr" "ifencei" ];
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+ rv64gc = [];
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+ riscv64-gc = [ "compressed" ] ++ features.riscv64-g;
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+ rv64gc_zba = [];
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+ riscv64-gcv = [ "vector" ] ++ features.riscv64-gc;
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+ rv64gc_zbb = [];
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+ rv64gc_zba_zbb = [];
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};
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};
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# a superior CPU has all the features of an inferior and is able to build and test code for it
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# a superior CPU has all the features of an inferior and is able to build and test code for it
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@@ -85,8 +100,23 @@ rec {
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@@ -92,8 +108,24 @@ rec {
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armv6 = [ ];
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armv6 = [ ];
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armv7-a = [ ];
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armv7-a = [ ];
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armv8-a = [ ];
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armv8-a = [ ];
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@ -46,9 +47,10 @@ index 94127fa9..5253e4bb 100644
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+ "armv9.3-a" = [ "armv9.2-a" "armv8.8-a" ] ++ inferiors."armv9.2-a" ++ inferiors."armv8.8-a";
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+ "armv9.3-a" = [ "armv9.2-a" "armv8.8-a" ] ++ inferiors."armv9.2-a" ++ inferiors."armv8.8-a";
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mips32 = [ ];
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mips32 = [ ];
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loongson2f = [ ];
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loongson2f = [ ];
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+ riscv64-g = [ ];
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+ rv64gc = [ ];
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+ riscv64-gc = [ "riscv64-g" ] ++ inferiors.riscv64-g;
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+ rv64gc_zba = [ "rv64gc" ] ++ inferiors.rv64gc;
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+ riscv64-gcv = [ "riscv64-gc" ] ++ inferiors.riscv64-gc;
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+ rv64gc_zbb = [ "rv64gc" ] ++ inferiors.rv64gc;
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+ rv64gc_zba_zbb = [ "rv64gc" "rv64gc_zba" "rv64gc_zbb" ];
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};
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};
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predicates = let
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predicates = let
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