darkkirb/per-system-optim
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add riscv

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This commit is contained in:
Charlotte 🦝 Delenk 2023-06-18 16:25:18 +01:00
parent 6d39c62f2a
commit 9b7255c188
Signed by: darkkirb
GPG key ID: AB2BD8DAF2E37122
3 changed files with 19 additions and 10 deletions
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6
default.nix
View file

@ -10,6 +10,7 @@
localSystems = rec {
x86_64-linux.system = "x86_64-linux";
aarch64-linux.system = "aarch64-linux";
riscv64-linux.system = "riscv64-linux";
default.system = system;
skylake =
x86_64-linux
@ -36,6 +37,11 @@
gcc.arch = "znver2";
gcc.tune = "znver2";
};
rv64_zba_zbb =
riscv64-linux
// {
gcc.arch = "rv64_zba_zbb";
};
};
pkgs-unpatched = import nixpkgs-unpatched' {
inherit system;

3
nixpkgs/eval.nix
View file

@ -1,4 +1,4 @@
{nixpkgs}: let
let
buildFor = system:
import ../. {
inherit nixpkgs system;
@ -7,4 +7,5 @@
in {
x86_64-linux = (buildFor "x86_64-linux").nixpkgs;
aarch64-linux = (buildFor "aarch64-linux").nixpkgs;
riscv64-linux = (buildFor "riscv64-linux").nixpkgs;
}

20
nixpkgs/nixpkgs.patch
View file

@ -1,8 +1,8 @@
diff --git a/lib/systems/architectures.nix b/lib/systems/architectures.nix
index 94127fa9..5253e4bb 100644
index 57b9184ca60..37d12ac687f 100644
--- a/lib/systems/architectures.nix
+++ b/lib/systems/architectures.nix
@@ -32,9 +32,24 @@ rec {
@@ -32,9 +32,25 @@ rec {
armv5te = [ ];
armv6 = [ ];
armv7-a = [ ];
@ -22,13 +22,14 @@ index 94127fa9..5253e4bb 100644
+ "armv9.3-a" = [ "mops" ] ++ features."armv9.2-a";
mips32 = [ ];
loongson2f = [ ];
+ riscv64-g = [ "multiply" "atomic" "float" "double" "csr" "ifencei" ];
+ riscv64-gc = [ "compressed" ] ++ features.riscv64-g;
+ riscv64-gcv = [ "vector" ] ++ features.riscv64-gc;
+ rv64gc = [];
+ rv64gc_zba = [];
+ rv64gc_zbb = [];
+ rv64gc_zba_zbb = [];
};
# a superior CPU has all the features of an inferior and is able to build and test code for it
@@ -85,8 +100,23 @@ rec {
@@ -92,8 +108,24 @@ rec {
armv6 = [ ];
armv7-a = [ ];
armv8-a = [ ];
@ -46,9 +47,10 @@ index 94127fa9..5253e4bb 100644
+ "armv9.3-a" = [ "armv9.2-a" "armv8.8-a" ] ++ inferiors."armv9.2-a" ++ inferiors."armv8.8-a";
mips32 = [ ];
loongson2f = [ ];
+ riscv64-g = [ ];
+ riscv64-gc = [ "riscv64-g" ] ++ inferiors.riscv64-g;
+ riscv64-gcv = [ "riscv64-gc" ] ++ inferiors.riscv64-gc;
+ rv64gc = [ ];
+ rv64gc_zba = [ "rv64gc" ] ++ inferiors.rv64gc;
+ rv64gc_zbb = [ "rv64gc" ] ++ inferiors.rv64gc;
+ rv64gc_zba_zbb = [ "rv64gc" "rv64gc_zba" "rv64gc_zbb" ];
};
predicates = let