darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
old-cross-binutils/sim/mips/Makefile.in
Andrew Bennett 8e394ffc7a [PATCH] Add micromips support to the MIPS simulator 
2015-09-25  Andrew Bennett  <andrew.bennett@imgtec.com>
 	      Ali Lown  <ali.lown@imgtec.com>

	sim/common/
	* sim-bits.h (EXTEND6): New macro.
	(EXTEND12): New macro.
	(EXTEND25): New macro.

	sim/mips/
	* Makefile.in (tmp-micromips): New rule.
	(tmp-mach-multi): Add support for micromips.
	* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
	that works for both mips64 and micromips64.
	(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
	micromips32.
	Add build support for micromips.
	* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
	do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
	do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
	do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
	do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
	do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
	do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
	do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
	Refactored instruction code to use these functions.
	* dsp2.igen: Refactored instruction code to use the new functions.
	* interp.c (decode_coproc): Refactored to work with any instruction
	encoding.
	(isa_mode): New variable
	(RSVD_INSTRUCTION): Changed to 0x00000039.
	* m16.igen (BREAK16): Refactored instruction to use do_break16.
	(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
	* micromips.dc: New file.
	* micromips.igen: New file.
	* micromips16.dc: New file.
	* micromipsdsp.igen: New file.
	* micromipsrun.c: New file.
	* mips.igen (do_swc1): Changed to work with any instruction encoding.
	(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
	do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
	do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
	do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
	do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
	do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
	do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
	do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
	do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
	do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
	do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
	do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
	do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
	do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
	do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
	do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
	do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
	do_trunc_fmt): New functions, refactored from existing instructions.
	Refactored instruction code to use these functions.
	(RSVD): Changed to use new reserved instruction.
	(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
	check_fmt_p, check_fpu, do_load_double, do_store_double):  Added micromips32
	and micromips64 models.
	Added include for micromips.igen and micromipsdsp.igen
	Add micromips32 and micromips64 models.
	(DecodeCoproc): Updated to use new macro definition.
	* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
	do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
	do_seb, do_seh do_rdhwr, do_wsbh): New functions.
	Refactored instruction code to use these functions.
	* sim-main.h (CP0_operation): New enum.
	(DecodeCoproc): Updated macro.
	(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
	MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
	ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
	(sim_state): Add isa_mode field.

	sim/testsuite/sim/mips/
       * basic.exp (run_micromips_test, run_sim_tests): New functions
	Add support for micromips tests.
	* hilo-hazard-4.s: New file.
	* testutils.inc (_dowrite): Changed reserved instruction encoding.
	(writemsg): Moved the la and li instructions before the data they are
	assigned to, which prevents a bug where MIPS32 relocations are used instead
	of micromips relocations when building for micromips.
2015-09-25 15:52:18 +01:00

650 lines
19 KiB
Makefile
Raw Blame History

# Makefile template for Configure for the MIPS simulator.
# Written by Cygnus Support.
SHELL = @SHELL@
## COMMON_PRE_CONFIG_FRAG
srcdir=@srcdir@
srcroot=$(srcdir)/../../
# Object files created by various simulator generators.
SIM_IGEN_OBJ = \
support.o \
itable.o \
semantics.o \
idecode.o \
icache.o \
@mips_igen_engine@ \
irun.o \
SIM_M16_OBJ = \
m16_support.o \
m16_semantics.o \
m16_idecode.o \
m16_icache.o \
\
m32_support.o \
m32_semantics.o \
m32_idecode.o \
m32_icache.o \
\
itable.o \
m16run.o \
SIM_MICROMIPS_OBJ = \
micromips16_support.o \
micromips16_semantics.o \
micromips16_idecode.o \
micromips16_icache.o \
\
micromips32_support.o \
micromips32_semantics.o \
micromips32_idecode.o \
micromips32_icache.o \
\
micromips_m32_support.o \
micromips_m32_semantics.o \
micromips_m32_idecode.o \
micromips_m32_icache.o \
\
itable.o \
micromipsrun.o \
SIM_MULTI_OBJ = @sim_multi_obj@ \
itable.o \
multi-run.o \
MIPS_EXTRA_LIBS = @mips_extra_libs@
SIM_OBJS = \
interp.o \
$(SIM_@sim_gen@_OBJ) \
$(SIM_NEW_COMMON_OBJS) \
cp1.o \
mdmx.o \
dsp.o \
sim-main.o \
sim-hload.o \
sim-stop.o \
sim-resume.o \
sim-reason.o \
# List of flags to always pass to $(CC).
SIM_SUBTARGET=@SIM_SUBTARGET@
SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
SIM_EXTRA_CLEAN = clean-extra
SIM_EXTRA_DISTCLEAN = distclean-extra
SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
## COMMON_POST_CONFIG_FRAG
interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
m16run.o: sim-main.h m16_idecode.h m32_idecode.h m16run.c $(SIM_EXTRA_DEPS)
micromipsrun.o: sim-main.h micromips16_idecode.h micromips32_idecode.h \
micromips_m32_idecode.h micromipsrun.c $(SIM_EXTRA_DEPS)
multi-run.o: multi-include.h tmp-mach-multi
../igen/igen:
cd ../igen && $(MAKE)
IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
IGEN_INSN=$(srcdir)/mips.igen
IGEN_DC=$(srcdir)/mips.dc
M16_DC=$(srcdir)/m16.dc
MICROMIPS32_DC=$(srcdir)/micromips.dc
MICROMIPS16_DC=$(srcdir)/micromips16.dc
IGEN_INCLUDE=\
$(srcdir)/micromipsdsp.igen \
$(srcdir)/micromips.igen \
$(srcdir)/m16.igen \
$(srcdir)/m16e.igen \
$(srcdir)/mdmx.igen \
$(srcdir)/mips3d.igen \
$(srcdir)/sb1.igen \
$(srcdir)/tx.igen \
$(srcdir)/vr.igen \
$(srcdir)/dsp.igen \
$(srcdir)/dsp2.igen \
$(srcdir)/mips3264r2.igen \
# NB: Since these can be built by a number of generators, care
# must be taken to ensure that they are only dependant on
# one of those generators.
BUILT_SRC_FROM_GEN = \
itable.h \
itable.c \
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
SIM_MICROMIPS_ALL = tmp-micromips
SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
BUILT_SRC_FROM_IGEN = \
icache.h \
icache.c \
idecode.h \
idecode.c \
semantics.h \
semantics.c \
model.h \
model.c \
support.h \
support.c \
engine.h \
engine.c \
irun.c \
$(BUILT_SRC_FROM_IGEN): tmp-igen
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-x \
-n icache.h -hc tmp-icache.h \
-n icache.c -c tmp-icache.c \
-n semantics.h -hs tmp-semantics.h \
-n semantics.c -s tmp-semantics.c \
-n idecode.h -hd tmp-idecode.h \
-n idecode.c -d tmp-idecode.c \
-n model.h -hm tmp-model.h \
-n model.c -m tmp-model.c \
-n support.h -hf tmp-support.h \
-n support.c -f tmp-support.c \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
-n engine.h -he tmp-engine.h \
-n engine.c -e tmp-engine.c \
-n irun.c -r tmp-irun.c
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c
$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
touch tmp-igen
BUILT_SRC_FROM_M16 = \
m16_icache.h \
m16_icache.c \
m16_idecode.h \
m16_idecode.c \
m16_semantics.h \
m16_semantics.c \
m16_model.h \
m16_model.c \
m16_support.h \
m16_support.c \
\
m32_icache.h \
m32_icache.c \
m32_idecode.h \
m32_idecode.c \
m32_semantics.h \
m32_semantics.c \
m32_model.h \
m32_model.c \
m32_support.h \
m32_support.c \
$(BUILT_SRC_FROM_M16): tmp-m16
tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_m16_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 16 \
-H 15 \
-i $(IGEN_INSN) \
-o $(M16_DC) \
-P m16_ \
-x \
-n m16_icache.h -hc tmp-icache.h \
-n m16_icache.c -c tmp-icache.c \
-n m16_semantics.h -hs tmp-semantics.h \
-n m16_semantics.c -s tmp-semantics.c \
-n m16_idecode.h -hd tmp-idecode.h \
-n m16_idecode.c -d tmp-idecode.c \
-n m16_model.h -hm tmp-model.h \
-n m16_model.c -m tmp-model.c \
-n m16_support.h -hf tmp-support.h \
-n m16_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m16_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m16_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m16_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m16_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-P m32_ \
-x \
-n m32_icache.h -hc tmp-icache.h \
-n m32_icache.c -c tmp-icache.c \
-n m32_semantics.h -hs tmp-semantics.h \
-n m32_semantics.c -s tmp-semantics.c \
-n m32_idecode.h -hd tmp-idecode.h \
-n m32_idecode.c -d tmp-idecode.c \
-n m32_model.h -hm tmp-model.h \
-n m32_model.c -m tmp-model.c \
-n m32_support.h -hf tmp-support.h \
-n m32_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
m32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
m32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m32_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-Wnowidth \
@sim_igen_flags@ @sim_m16_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-m16
BUILT_SRC_FROM_MICROMIPS = \
micromips16_icache.h \
micromips16_icache.c \
micromips16_idecode.h \
micromips16_idecode.c \
micromips16_semantics.h \
micromips16_semantics.c \
micromips16_model.h \
micromips16_model.c \
micromips16_support.h \
micromips16_support.c \
\
micromips32_icache.h \
micromips32_icache.c \
micromips32_idecode.h \
micromips32_idecode.c \
micromips32_semantics.h \
micromips32_semantics.c \
micromips32_model.h \
micromips32_model.c \
micromips32_support.h \
micromips32_support.c \
\
micromips_m32_icache.h \
micromips_m32_icache.c \
micromips_m32_idecode.h \
micromips_m32_idecode.c \
micromips_m32_semantics.h \
micromips_m32_semantics.c \
micromips_m32_model.h \
micromips_m32_model.c \
micromips_m32_support.h \
micromips_m32_support.c \
$(BUILT_SRC_FROM_MICROMIPS): tmp-micromips
tmp-micromips: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_micromips16_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 16 \
-H 15 \
-i $(IGEN_INSN) \
-o $(MICROMIPS16_DC) \
-P micromips16_ \
-x \
-n micromips16_icache.h -hc tmp-icache.h \
-n micromips16_icache.c -c tmp-icache.c \
-n micromips16_semantics.h -hs tmp-semantics.h \
-n micromips16_semantics.c -s tmp-semantics.c \
-n micromips16_idecode.h -hd tmp-idecode.h \
-n micromips16_idecode.c -d tmp-idecode.c \
-n micromips16_model.h -hm tmp-model.h \
-n micromips16_model.c -m tmp-model.c \
-n micromips16_support.h -hf tmp-support.h \
-n micromips16_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
micromips16_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
micromips16_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
micromips16_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
micromips16_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
micromips16_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
micromips16_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
micromips16_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
micromips16_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
micromips16_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
micromips16_support.c
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_micromips_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(MICROMIPS32_DC) \
-P micromips32_ \
-x \
-n micromips32_icache.h -hc tmp-icache.h \
-n micromips32_icache.c -c tmp-icache.c \
-n micromips32_semantics.h -hs tmp-semantics.h \
-n micromips32_semantics.c -s tmp-semantics.c \
-n micromips32_idecode.h -hd tmp-idecode.h \
-n micromips32_idecode.c -d tmp-idecode.c \
-n micromips32_model.h -hm tmp-model.h \
-n micromips32_model.c -m tmp-model.c \
-n micromips32_support.h -hf tmp-support.h \
-n micromips32_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
micromips32_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
micromips32_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
micromips32_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
micromips32_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
micromips32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
micromips32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
micromips32_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
micromips32_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
micromips32_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
micromips32_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-P micromips_m32_ \
-x \
-n micromips_m32_icache.h -hc tmp-icache.h \
-n micromips_m32_icache.c -c tmp-icache.c \
-n micromips_m32_semantics.h -hs tmp-semantics.h \
-n micromips_m32_semantics.c -s tmp-semantics.c \
-n micromips_m32_idecode.h -hd tmp-idecode.h \
-n micromips_m32_idecode.c -d tmp-idecode.c \
-n micromips_m32_model.h -hm tmp-model.h \
-n micromips_m32_model.c -m tmp-model.c \
-n micromips_m32_support.h -hf tmp-support.h \
-n micromips_m32_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
micromips_m32_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
micromips_m32_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
micromips_m32_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
micromips_m32_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
micromips_m32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
micromips_m32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
micromips_m32_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
micromips_m32_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
micromips_m32_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
micromips_m32_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-Wnowidth \
@sim_igen_flags@ @sim_micromips_flags@ @sim_micromips16_flags@\
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-micromips
BUILT_SRC_FROM_MULTI = @sim_multi_src@
SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
$(BUILT_SRC_FROM_MULTI): tmp-multi
tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
for t in $(SIM_MULTI_IGEN_CONFIGS); do \
p=`echo $${t} | sed -e 's/:.*//'` ; \
m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
f=`echo $${t} | sed -e 's/.*://'` ; \
case $${p} in \
micromips16*) e="-B 16 -H 15 -o $(MICROMIPS16_DC) -F 16" ;; \
micromips32* | micromips64*) \
e="-B 32 -H 31 -o $(MICROMIPS32_DC) -F $${f}" ;; \
micromips_m32*) \
e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
micromips_m64*) \
e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
*) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
esac; \
../igen/igen \
$(IGEN_TRACE) \
$${e} \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-N 0 \
-M $${m} \
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-P $${p}_ \
-x \
-n $${p}_icache.h -hc tmp-icache.h \
-n $${p}_icache.c -c tmp-icache.c \
-n $${p}_semantics.h -hs tmp-semantics.h \
-n $${p}_semantics.c -s tmp-semantics.c \
-n $${p}_idecode.h -hd tmp-idecode.h \
-n $${p}_idecode.c -d tmp-idecode.c \
-n $${p}_model.h -hm tmp-model.h \
-n $${p}_model.c -m tmp-model.c \
-n $${p}_support.h -hf tmp-support.h \
-n $${p}_support.c -f tmp-support.c \
-n $${p}_engine.h -he tmp-engine.h \
-n $${p}_engine.c -e tmp-engine.c \
|| exit; \
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
$${p}_icache.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
$${p}_icache.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
$${p}_idecode.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
$${p}_idecode.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
$${p}_semantics.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
$${p}_semantics.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
$${p}_model.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
$${p}_model.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
$${p}_support.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
$${p}_support.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h \
$${p}_engine.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c \
$${p}_engine.c ; \
done
touch tmp-mach-multi
tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-Wnowidth \
-N 0 \
@sim_multi_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-itable-multi
tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsrun.c
for t in $(SIM_MULTI_IGEN_CONFIGS); do \
case $${t} in \
m16*) \
m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
sed < $(srcdir)/m16run.c > tmp-run \
-e "s/^sim_/m16$${m}_/" \
-e "s/m16_/m16$${m}_/" \
-e "s/m32_/m32$${m}_/" ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
m16$${m}_run.c ; \
;;\
micromips32*) \
m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \
sed < $(srcdir)/micromipsrun.c > tmp-run \
-e "s/^sim_/micromips32$${m}_/" \
-e "s/micromips16_/micromips16$${m}_/" \
-e "s/micromips32_/micromips32$${m}_/" \
-e "s/m32_/m32$${m}_/" ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
micromips$${m}_run.c ; \
;;\
micromips64*) \
m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \
sed < $(srcdir)/micromipsrun.c > tmp-run \
-e "s/^sim_/micromips64$${m}_/" \
-e "s/micromips16_/micromips16$${m}_/" \
-e "s/micromips32_/micromips64$${m}_/" \
-e "s/m32_/m64$${m}_/" ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
micromips$${m}_run.c ; \
;;\
esac \
done
touch tmp-run-multi
clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
rm -f $(BUILT_SRC_FROM_MICROMIPS)
rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f micromips16*.o micromips32*.o m16*.o m32*.o itable*.o
distclean-extra:
rm -f multi-include.h multi-run.c
Reference in a new issue View git blame Copy permalink