fe56b6cece
* arm-dis.c (coprocessor): Print the LDC and STC versions of the
LFM and SFM instructions as comments,.
Improve consistency of formatting for instructions displayed as
comments and decimal values displayed with their hexadecimal
equivalents.
Formatting tidy ups.
Updated expected disassembler regexps.
56 lines
1.5 KiB
Makefile
56 lines
1.5 KiB
Makefile
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tmpdir/mixed-app-v5: file format elf32-(little|big)arm
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architecture: arm, flags 0x00000112:
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EXEC_P, HAS_SYMS, D_PAGED
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start address 0x.*
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Disassembly of section .plt:
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.* <.plt>:
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.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
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.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x1c>
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.*: e08fe00e add lr, pc, lr
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.*: e5bef008 ldr pc, \[lr, #8\]!
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.*: .*
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.*: e28fc6.* add ip, pc, #.*
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.*: e28cca.* add ip, ip, #.* ; 0x.*
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.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
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.*: e28fc6.* add ip, pc, #.*
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.*: e28cca.* add ip, ip, #.* ; 0x.*
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.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
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Disassembly of section .text:
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.* <_start>:
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.*: e1a0c00d mov ip, sp
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.*: e92dd800 push {fp, ip, lr, pc}
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.*: eb000004 bl .* <app_func>
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.*: e89d6800 ldm sp, {fp, sp, lr}
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.*: e12fff1e bx lr
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.*: e1a00000 nop ; \(mov r0, r0\)
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.*: e1a00000 nop ; \(mov r0, r0\)
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.*: e1a00000 nop ; \(mov r0, r0\)
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.* <app_func>:
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.*: e1a0c00d mov ip, sp
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.*: e92dd800 push {fp, ip, lr, pc}
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.*: ebfffff. bl .*
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.*: e89d6800 ldm sp, {fp, sp, lr}
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.*: e12fff1e bx lr
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.*: e1a00000 nop ; \(mov r0, r0\)
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.*: e1a00000 nop ; \(mov r0, r0\)
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.*: e1a00000 nop ; \(mov r0, r0\)
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.* <app_func2>:
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.*: e12fff1e bx lr
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.*: e1a00000 nop ; \(mov r0, r0\)
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.*: e1a00000 nop ; \(mov r0, r0\)
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.*: e1a00000 nop ; \(mov r0, r0\)
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.* <app_tfunc>:
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.*: b500 push {lr}
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.*: f7ff efc. blx .* <_start-0x..>
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.*: bd00 pop {pc}
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.*: 4770 bx lr
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.*: 46c0 nop ; \(mov r8, r8\)
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.*: 46c0 nop ; \(mov r8, r8\)
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.*: 46c0 nop ; \(mov r8, r8\)
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