bb51b65d68
* Makefile.in (SIM_OBJS): Add sim-reg.o, cgen-run.o, sim-stop.o. (SIM_EXTRA_DEPS): Add include/opcode/cgen.h. (INCLUDE_DEPS): Delete cpu-sim.h, include/opcode/cgen.h. (mloop.c): Build pseudo-basic-block version. Depend on stamp-cpu. (stamp-decode): Delete, build decode files with other cpu files. * arch.c,arch.h,cpuall.h: Regenerate. * cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate. * sem-switch.c,sem.c: Regenerate. * m32r-sim.h (M32R_MISC_PROFILE): New members load_regs, load_regs_pending. * m32r.c (m32rbf_fetch_register): Renamed from m32rb_fetch_register. (m32rbf_store_register,m32rbf_h_cr_get,m32rbf_h_cr_set, m32rbf_h_psw_get,m32rbf_h_psw_set,m32rbf_h_accum_get, m32rbf_h_accum_set): Likewise. (m32r_model_{init,update}_insn_cycles): Delete. (m32rbf_model_insn_{before,after}): New fns. (m32r_model_record_cti,m32r_model_record_cycles): Delete. (m32rb_model_mark_get_h_gr,m32rb_model_mark_set_h_gr): Delete. (m32rb_model_mark_busy_reg,m32rb_model_mark_unbusy_reg): Delete. (check_load_stall): New fn. (m32rbf_model_m32r_d_u_{exec,cmp,mac,cti,load,store}): New fns. (m32rbf_model_test_u_exec): New fn. * mloop.in: Rewrite, use pbb support. * sim-if.c (sim_stop,sim_sync_stop,sim_resume): Delete. (sim_fetch_register,sim_store_register): Delete. * sim-main.h (CIA_GET,CIA_SET): Fix. (SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Delete. * tconfig.in (WITH_SCACHE_PBB): Define. (WITH_SCACHE_PBB_M32RBF): Define. * traps.c (sim_engine_invalid_insn): Renamed from ..._illegal_.... (m32r_trap): Pass pc to sim_engine_halt. * configure.in (SIM_AC_OPTION_SCACHE): Change 1024 to 16384. * configure: Regenerate. start-sanitize-m32rx * Makefile.in (M32RX_OBJS): Delete semx.o, add extract.o. (mloopx.c): Build pseudo-basic-block version. Depend on stamp-xcpu. (semx.o): Delete. (extractx.o): Add. (stamp-xdecode): Delete, build decode files with other cpu files. * cpux.c,cpux.h,decodex.c,decodex.h,modelx.c: Regenerate. * readx.c: Delete. * semx.c: Delete. * extractx.c: New file. * semx-switch.c: New file. * m32r-sim.h (BRANCH_NEW_PC): Delete. (SEM_SKIP_INSN): New macro. * m32rx.c (m32rxf_fetch_register): Renamed from m32rx_fetch_register. (m32rxf_store_register,m32rxf_h_cr_get,m32rxf_h_cr_set, m32rxf_h_psw_get,m32rxf_h_psw_set,m32rxf_h_accum_get, m32rxf_h_accum_set,m32rxf_h_accums_get,m32rxf_h_accums_set): Likewise. (m32rxf_model_insn_{before,after}): New fns. (m32rx_model_mark_get_h_gr,m32rx_model_mark_set_h_gr): Delete. (m32rx_model_mark_busy_reg,m32rx_model_mark_unbusy_reg): Delete. (check_load_stall): New fn. (m32rxf_model_m32rx_u_{exec,cmp,mac,cti,load,store}): New fns. * mloopx.in: Rewrite, use pbb support. * tconfig.in (WITH_SCACHE_PBB_M32RXF): Define. (WITH_SEM_SWITCH_FULL): Change from 0 to 1. end-sanitize-m32rx
162 lines
5.3 KiB
Makefile
162 lines
5.3 KiB
Makefile
# Makefile template for Configure for the m32r simulator
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# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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# Contributed by Cygnus Support.
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#
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# This file is part of GDB, the GNU debugger.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program; if not, write to the Free Software Foundation, Inc.,
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# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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## COMMON_PRE_CONFIG_FRAG
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M32R_OBJS = m32r.o cpu.o decode.o extract.o sem.o model.o mloop.o
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# start-sanitize-m32rx
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M32RX_OBJS = m32rx.o cpux.o decodex.o extractx.o modelx.o mloopx.o
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# end-sanitize-m32rx
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CONFIG_DEVICES = dv-sockser.o
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CONFIG_DEVICES =
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SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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sim-cpu.o \
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sim-hload.o \
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sim-hrw.o \
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sim-model.o \
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sim-reg.o \
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cgen-utils.o cgen-trace.o cgen-scache.o \
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cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
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sim-if.o arch.o \
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$(M32R_OBJS) \
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$(start-sanitize-m32rx) \
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$(M32RX_OBJS) \
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$(end-sanitize-m32rx) \
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traps.o devices.o \
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$(CONFIG_DEVICES)
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# Extra headers included by sim-main.h.
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SIM_EXTRA_DEPS = \
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$(srcdir)/../common/cgen-types.h \
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$(srcdir)/../common/cgen-sim.h \
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$(srcdir)/../common/cgen-trace.h \
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arch.h cpuall.h m32r-sim.h cpu-opc.h \
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$(srcdir)/../../include/opcode/cgen.h
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SIM_EXTRA_CFLAGS =
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SIM_RUN_OBJS = nrun.o
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SIM_EXTRA_CLEAN = m32r-clean
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# This selects the m32r newlib/libgloss syscall definitions.
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NL_TARGET = -DNL_TARGET_m32r
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## COMMON_POST_CONFIG_FRAG
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arch = m32r
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MAIN_INCLUDE_DEPS = \
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sim-main.h \
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$(srcdir)/../common/sim-config.h \
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$(srcdir)/../common/sim-base.h \
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$(srcdir)/../common/sim-basics.h \
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$(srcdir)/../common/sim-module.h \
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$(srcdir)/../common/sim-trace.h \
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$(srcdir)/../common/sim-profile.h \
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tconfig.h
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INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS)
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OPS_INCLUDE_DEPS = \
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$(srcdir)/../common/cgen-mem.h \
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$(srcdir)/../common/cgen-ops.h
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sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h
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arch.o: arch.c $(INCLUDE_DEPS)
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devices.o: devices.c $(INCLUDE_DEPS)
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# M32R objs
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m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
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# FIXME: Use of `mono' is wip.
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mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
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rm -f mloop.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
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-mono -fast -pbb -switch sem-switch.c \
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m32rbf $(srcdir)/mloop.in \
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| sed -e 's/@cpu@/m32rbf/' -e 's/@CPU@/M32RBF/' >mloop.c
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mloop.o: mloop.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) stamp-cpu
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cpu.o: cpu.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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decode.o: decode.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
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extract.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
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sem.o: sem.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
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model.o: model.c $(INCLUDE_DEPS) cpu.h decode.h
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# start-sanitize-m32rx
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# M32RX objs
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m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
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# FIXME: Use of `mono' is wip.
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mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
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rm -f mloopx.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
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-mono -no-fast -pbb -parallel -switch semx-switch.c \
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m32rxf $(srcdir)/mloopx.in \
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| sed -e 's/@cpu@/m32rxf/' -e 's/@CPU@/M32RXF/' >mloopx.c
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mloopx.o: mloopx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) stamp-xcpu
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cpux.o: cpux.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
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decodex.o: decodex.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
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extractx.o: extractx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
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#semx.o: semx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
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modelx.o: modelx.c $(INCLUDE_DEPS) cpux.h decodex.h
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# end-sanitize-m32rx
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m32r-clean:
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rm -f mloop.c stamp-arch stamp-cpu
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# start-sanitize-m32rx
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rm -f mloopx.c stamp-xcpu
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# end-sanitize-m32rx
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rm -f tmp-*
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# start-sanitize-cygnus
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# cgen support, enable with --enable-cgen-maint
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CGEN_MAINT = ; @true
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# The following line is commented in or out depending upon --enable-cgen-maint.
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@CGEN_MAINT@CGEN_MAINT =
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stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS)
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touch stamp-arch
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arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
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@true
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stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=m32rbf mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
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touch stamp-cpu
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cpu.h extract.c sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
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@true
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# end-sanitize-cygnus
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# start-sanitize-m32rx
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stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEMSW)"
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touch stamp-xcpu
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cpux.h extractx.c semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
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@true
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# end-sanitize-m32rx
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