fcea6f2092
(insert_normal): Progress on handling ! CGEN_INT_INSN_P. (insert_insn_normal): Update handling of CGEN_INT_INSN_P. (@arch@_cgen_assemble_insn): Update type of `buf' arg. * cgen-dis.in (extract_1): New function. (extract_normal): buf_ctrl renamed to ex_info, update type. Progress on handling of CGEN_INT_INSN_P. (extract_insn_normal): buf_ctrl renamed to ex_info, update type. Update handling of CGEN_INT_INSN_P. Handle errors from @arch@_cgen_extract_operand. (print_insn): Renamed from print_int_insn. Handle ! CGEN_INT_INSN_P. (default_print_insn): Renamed from print_insn. Handle ! CGEN_INT_INSN_P. (print_insn_@arch@): Handle error returns from print_insn. * cgen-opc.in (cgen_get_insn_value, cgen_put_insn_value): New fns. (@arch@_cgen_lookup_insn): Update handling of CGEN_INT_INSN_P. (@arch@_cgen_lookup_get_insn_operands): Ditto. * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
266 lines
7 KiB
C
266 lines
7 KiB
C
/* Generic opcode table support for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS USED TO GENERATE @prefix@-opc.c.
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Copyright (C) 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "libiberty.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "@prefix@-opc.h"
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#include "opintl.h"
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/* The hash functions are recorded here to help keep assembler code out of
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the disassembler and vice versa. */
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static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
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static unsigned int asm_hash_insn PARAMS ((const char *));
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static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
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static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
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/* Cover function to read and properly byteswap an insn value. */
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CGEN_INSN_INT
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cgen_get_insn_value (od, buf, length)
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CGEN_OPCODE_DESC od;
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unsigned char *buf;
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int length;
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{
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CGEN_INSN_INT value;
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switch (length)
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{
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case 8:
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value = *buf;
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break;
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case 16:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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value = bfd_getb16 (buf);
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else
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value = bfd_getl16 (buf);
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break;
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case 32:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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value = bfd_getb32 (buf);
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else
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value = bfd_getl32 (buf);
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break;
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default:
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abort ();
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}
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return value;
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}
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/* Cover function to store an insn value properly byteswapped. */
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void
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cgen_put_insn_value (od, buf, length, value)
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CGEN_OPCODE_DESC od;
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unsigned char *buf;
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int length;
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CGEN_INSN_INT value;
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{
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switch (length)
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{
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case 8:
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buf[0] = value;
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break;
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case 16:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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bfd_putb16 (value, buf);
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else
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bfd_putl16 (value, buf);
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break;
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case 32:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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bfd_putb32 (value, buf);
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else
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bfd_putl32 (value, buf);
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break;
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default:
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abort ();
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}
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}
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/* Look up instruction INSN_VALUE and extract its fields.
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INSN, if non-null, is the insn table entry.
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Otherwise INSN_VALUE is examined to compute it.
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LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
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0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
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If INSN != NULL, LENGTH must be valid.
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ALIAS_P is non-zero if alias insns are to be included in the search.
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The result a pointer to the insn table entry, or NULL if the instruction
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wasn't recognized. */
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const CGEN_INSN *
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@arch@_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN *insn;
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CGEN_INSN_BYTES insn_value;
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int length;
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CGEN_FIELDS *fields;
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int alias_p;
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{
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unsigned char buf[16];
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unsigned char *bufp;
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unsigned int base_insn;
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#if CGEN_INT_INSN_P
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CGEN_EXTRACT_INFO *info = NULL;
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#else
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CGEN_EXTRACT_INFO ex_info;
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CGEN_EXTRACT_INFO *info = &ex_info;
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#endif
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#if ! CGEN_INT_INSN_P
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ex_info.dis_info = NULL;
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ex_info.bytes = insn_value;
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ex_info.valid = -1;
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#endif
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if (!insn)
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{
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const CGEN_INSN_LIST *insn_list;
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#if CGEN_INT_INSN_P
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cgen_put_insn_value (od, buf, length, insn_value);
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bufp = buf;
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base_insn = insn_value; /*???*/
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#else
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base_insn = cgen_get_insn_value (od, buf, length);
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bufp = insn_value;
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#endif
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/* The instructions are stored in hash lists.
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Pick the first one and keep trying until we find the right one. */
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insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
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while (insn_list != NULL)
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{
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insn = insn_list->insn;
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if (alias_p
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|| ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
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{
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/* Basic bit mask must be correct. */
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/* ??? May wish to allow target to defer this check until the
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extract handler. */
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if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
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{
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/* ??? 0 is passed for `pc' */
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int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
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insn_value, fields,
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(bfd_vma) 0);
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if (elength > 0)
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{
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/* sanity check */
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if (length != 0 && length != elength)
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abort ();
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return insn;
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}
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}
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}
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insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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}
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}
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else
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{
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/* Sanity check: can't pass an alias insn if ! alias_p. */
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if (! alias_p
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&& CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
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abort ();
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/* Sanity check: length must be correct. */
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if (length != CGEN_INSN_BITSIZE (insn))
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abort ();
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/* ??? 0 is passed for `pc' */
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length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
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(bfd_vma) 0);
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/* Sanity check: must succeed.
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Could relax this later if it ever proves useful. */
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if (length == 0)
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abort ();
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return insn;
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}
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return NULL;
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}
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/* Fill in the operand instances used by INSN whose operands are FIELDS.
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INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
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in. */
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void
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@arch@_cgen_get_insn_operands (od, insn, fields, indices)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN * insn;
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const CGEN_FIELDS * fields;
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int *indices;
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{
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const CGEN_OPERAND_INSTANCE *opinst;
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int i;
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for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
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opinst != NULL
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&& CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
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++i, ++opinst)
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{
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const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
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if (op == NULL)
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indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
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else
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indices[i] = @arch@_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
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fields);
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}
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}
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/* Cover function to @arch@_cgen_get_insn_operands when either INSN or FIELDS
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isn't known.
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The INSN, INSN_VALUE, and LENGTH arguments are passed to
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@arch@_cgen_lookup_insn unchanged.
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The result is the insn table entry or NULL if the instruction wasn't
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recognized. */
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const CGEN_INSN *
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@arch@_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN *insn;
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CGEN_INSN_BYTES insn_value;
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int length;
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int *indices;
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{
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CGEN_FIELDS fields;
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/* Pass non-zero for ALIAS_P only if INSN != NULL.
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If INSN == NULL, we want a real insn. */
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insn = @arch@_cgen_lookup_insn (od, insn, insn_value, length, &fields,
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insn != NULL);
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if (! insn)
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return NULL;
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@arch@_cgen_get_insn_operands (od, insn, &fields, indices);
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return insn;
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}
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