73 lines
3 KiB
C
73 lines
3 KiB
C
/* Target-dependent code for GDB, the GNU debugger.
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Copyright 2001
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#ifndef I386_TDEP_H
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#define I386_TDEP_H
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#define FPU_REG_RAW_SIZE 10
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#define XMM0_REGNUM FIRST_XMM_REGNUM
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#define FIRST_FPU_REGNUM FP0_REGNUM
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#define LAST_FPU_REGNUM (gdbarch_tdep (current_gdbarch)->last_fpu_regnum)
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#define FIRST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->first_xmm_regnum)
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#define LAST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->last_xmm_regnum)
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#define MXCSR_REGNUM (gdbarch_tdep (current_gdbarch)->mxcsr_regnum)
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#define FIRST_FPU_CTRL_REGNUM (gdbarch_tdep (current_gdbarch)->first_fpu_ctrl_regnum)
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#define LAST_FPU_CTRL_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
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/* All of these control registers (except for FCOFF and FDOFF) are
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sixteen bits long (at most) in the FPU, but are zero-extended to
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thirty-two bits in GDB's register file. This makes it easier to
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compute the size of the control register file, and somewhat easier
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to convert to and from the FSAVE instruction's 32-bit format. */
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/* FPU control word. */
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#define FCTRL_REGNUM (FIRST_FPU_CTRL_REGNUM)
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/* FPU status word. */
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#define FSTAT_REGNUM (FIRST_FPU_CTRL_REGNUM + 1)
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/* FPU register tag word. */
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#define FTAG_REGNUM (FIRST_FPU_CTRL_REGNUM + 2)
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/* FPU instruction's code segment selector 16 bits, called "FPU Instruction
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Pointer Selector" in the x86 manuals. */
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#define FCS_REGNUM (FIRST_FPU_CTRL_REGNUM + 3)
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/* FPU instruction's offset within segment ("Fpu Code OFFset"). */
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#define FCOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 4)
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/* FPU operand's data segment. */
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#define FDS_REGNUM (FIRST_FPU_CTRL_REGNUM + 5)
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/* FPU operand's offset within segment. */
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#define FDOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 6)
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/* FPU opcode, bottom eleven bits. */
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#define FOP_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
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/* i386 architecture specific information. */
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struct gdbarch_tdep
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{
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int last_fpu_regnum;
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int first_xmm_regnum;
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int last_xmm_regnum;
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int mxcsr_regnum; /* Streaming SIMD Extension control/status. */
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int first_fpu_ctrl_regnum;
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};
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#define IS_FP_REGNUM(n) (FIRST_FPU_REGNUM <= (n) && (n) <= LAST_FPU_REGNUM)
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#define IS_FPU_CTRL_REGNUM(n) (FIRST_FPU_CTRL_REGNUM <= (n) && (n) <= LAST_FPU_CTRL_REGNUM)
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#define IS_SSE_REGNUM(n) (FIRST_XMM_REGNUM <= (n) && (n) <= LAST_XMM_REGNUM)
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#endif
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