944 lines
22 KiB
C
944 lines
22 KiB
C
/* Disassemble SH instructions.
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Copyright (C) 1993-2015 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#define STATIC_TABLE
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#define DEFINE_TABLE
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#include "sh-opc.h"
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#include "dis-asm.h"
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#ifdef ARCH_all
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#define INCLUDE_SHMEDIA
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#endif
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static void
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print_movxy (const sh_opcode_info *op,
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int rn,
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int rm,
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fprintf_ftype fprintf_fn,
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void *stream)
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{
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int n;
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fprintf_fn (stream, "%s\t", op->name);
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for (n = 0; n < 2; n++)
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{
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switch (op->arg[n])
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{
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case A_IND_N:
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case AX_IND_N:
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case AXY_IND_N:
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case AY_IND_N:
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case AYX_IND_N:
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fprintf_fn (stream, "@r%d", rn);
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break;
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case A_INC_N:
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case AX_INC_N:
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case AXY_INC_N:
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case AY_INC_N:
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case AYX_INC_N:
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fprintf_fn (stream, "@r%d+", rn);
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break;
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case AX_PMOD_N:
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case AXY_PMOD_N:
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fprintf_fn (stream, "@r%d+r8", rn);
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break;
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case AY_PMOD_N:
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case AYX_PMOD_N:
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fprintf_fn (stream, "@r%d+r9", rn);
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break;
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case DSP_REG_A_M:
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fprintf_fn (stream, "a%c", '0' + rm);
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break;
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case DSP_REG_X:
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fprintf_fn (stream, "x%c", '0' + rm);
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break;
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case DSP_REG_Y:
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fprintf_fn (stream, "y%c", '0' + rm);
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break;
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case DSP_REG_AX:
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fprintf_fn (stream, "%c%c",
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(rm & 1) ? 'x' : 'a',
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(rm & 2) ? '1' : '0');
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break;
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case DSP_REG_XY:
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fprintf_fn (stream, "%c%c",
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(rm & 1) ? 'y' : 'x',
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(rm & 2) ? '1' : '0');
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break;
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case DSP_REG_AY:
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fprintf_fn (stream, "%c%c",
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(rm & 2) ? 'y' : 'a',
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(rm & 1) ? '1' : '0');
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break;
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case DSP_REG_YX:
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fprintf_fn (stream, "%c%c",
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(rm & 2) ? 'x' : 'y',
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(rm & 1) ? '1' : '0');
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break;
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default:
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abort ();
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}
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if (n == 0)
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fprintf_fn (stream, ",");
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}
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}
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/* Print a double data transfer insn. INSN is just the lower three
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nibbles of the insn, i.e. field a and the bit that indicates if
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a parallel processing insn follows.
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Return nonzero if a field b of a parallel processing insns follows. */
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static void
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print_insn_ddt (int insn, struct disassemble_info *info)
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{
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fprintf_ftype fprintf_fn = info->fprintf_func;
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void *stream = info->stream;
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/* If this is just a nop, make sure to emit something. */
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if (insn == 0x000)
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fprintf_fn (stream, "nopx\tnopy");
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/* If a parallel processing insn was printed before,
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and we got a non-nop, emit a tab. */
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if ((insn & 0x800) && (insn & 0x3ff))
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fprintf_fn (stream, "\t");
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/* Check if either the x or y part is invalid. */
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if (((insn & 0xc) == 0 && (insn & 0x2a0))
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|| ((insn & 3) == 0 && (insn & 0x150)))
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if (info->mach != bfd_mach_sh_dsp
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&& info->mach != bfd_mach_sh3_dsp)
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{
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static const sh_opcode_info *first_movx, *first_movy;
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const sh_opcode_info *op;
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int is_movy;
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if (! first_movx)
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{
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for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
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first_movx++;
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for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
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first_movy++;
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}
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is_movy = ((insn & 3) != 0);
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if (is_movy)
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op = first_movy;
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else
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op = first_movx;
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while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
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|| op->nibbles[3] != (unsigned) (insn & 0xf))
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op++;
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print_movxy (op,
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(4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
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+ 2 * is_movy
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+ 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
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(insn >> 6) & 3,
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fprintf_fn, stream);
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}
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else
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fprintf_fn (stream, ".word 0x%x", insn);
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else
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{
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static const sh_opcode_info *first_movx, *first_movy;
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const sh_opcode_info *opx, *opy;
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unsigned int insn_x, insn_y;
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if (! first_movx)
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{
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for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
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first_movx++;
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for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
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first_movy++;
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}
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insn_x = (insn >> 2) & 0xb;
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if (insn_x)
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{
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for (opx = first_movx; opx->nibbles[2] != insn_x;)
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opx++;
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print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
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fprintf_fn, stream);
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}
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insn_y = (insn & 3) | ((insn >> 1) & 8);
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if (insn_y)
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{
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if (insn_x)
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fprintf_fn (stream, "\t");
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for (opy = first_movy; opy->nibbles[2] != insn_y;)
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opy++;
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print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
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fprintf_fn, stream);
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}
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}
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}
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static void
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print_dsp_reg (int rm, fprintf_ftype fprintf_fn, void *stream)
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{
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switch (rm)
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{
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case A_A1_NUM:
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fprintf_fn (stream, "a1");
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break;
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case A_A0_NUM:
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fprintf_fn (stream, "a0");
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break;
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case A_X0_NUM:
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fprintf_fn (stream, "x0");
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break;
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case A_X1_NUM:
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fprintf_fn (stream, "x1");
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break;
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case A_Y0_NUM:
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fprintf_fn (stream, "y0");
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break;
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case A_Y1_NUM:
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fprintf_fn (stream, "y1");
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break;
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case A_M0_NUM:
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fprintf_fn (stream, "m0");
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break;
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case A_A1G_NUM:
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fprintf_fn (stream, "a1g");
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break;
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case A_M1_NUM:
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fprintf_fn (stream, "m1");
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break;
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case A_A0G_NUM:
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fprintf_fn (stream, "a0g");
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break;
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default:
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fprintf_fn (stream, "0x%x", rm);
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break;
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}
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}
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static void
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print_insn_ppi (int field_b, struct disassemble_info *info)
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{
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static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
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static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
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fprintf_ftype fprintf_fn = info->fprintf_func;
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void *stream = info->stream;
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unsigned int nib1, nib2, nib3;
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unsigned int altnib1, nib4;
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char *dc = NULL;
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const sh_opcode_info *op;
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if ((field_b & 0xe800) == 0)
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{
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fprintf_fn (stream, "psh%c\t#%d,",
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field_b & 0x1000 ? 'a' : 'l',
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(field_b >> 4) & 127);
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print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
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return;
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}
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if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
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{
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static char *du_tab[] = { "x0", "y0", "a0", "a1" };
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static char *se_tab[] = { "x0", "x1", "y0", "a1" };
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static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
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static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
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if (field_b & 0x2000)
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fprintf_fn (stream, "p%s %s,%s,%s\t",
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(field_b & 0x1000) ? "add" : "sub",
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sx_tab[(field_b >> 6) & 3],
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sy_tab[(field_b >> 4) & 3],
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du_tab[(field_b >> 0) & 3]);
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else if ((field_b & 0xf0) == 0x10
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&& info->mach != bfd_mach_sh_dsp
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&& info->mach != bfd_mach_sh3_dsp)
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fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
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else if ((field_b & 0xf3) != 0)
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fprintf_fn (stream, ".word 0x%x\t", field_b);
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fprintf_fn (stream, "pmuls%c%s,%s,%s",
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field_b & 0x2000 ? ' ' : '\t',
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se_tab[(field_b >> 10) & 3],
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sf_tab[(field_b >> 8) & 3],
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sg_tab[(field_b >> 2) & 3]);
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return;
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}
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nib1 = PPIC;
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nib2 = field_b >> 12 & 0xf;
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nib3 = field_b >> 8 & 0xf;
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nib4 = field_b >> 4 & 0xf;
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switch (nib3 & 0x3)
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{
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case 0:
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dc = "";
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nib1 = PPI3;
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break;
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case 1:
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dc = "";
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break;
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case 2:
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dc = "dct ";
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nib3 -= 1;
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break;
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case 3:
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dc = "dcf ";
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nib3 -= 2;
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break;
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}
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if (nib1 == PPI3)
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altnib1 = PPI3NC;
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else
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altnib1 = nib1;
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for (op = sh_table; op->name; op++)
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{
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if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
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&& op->nibbles[2] == nib2
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&& op->nibbles[3] == nib3)
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{
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int n;
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switch (op->nibbles[4])
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{
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case HEX_0:
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break;
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case HEX_XX00:
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if ((nib4 & 3) != 0)
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continue;
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break;
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case HEX_1:
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if ((nib4 & 3) != 1)
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continue;
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break;
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case HEX_00YY:
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if ((nib4 & 0xc) != 0)
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continue;
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break;
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case HEX_4:
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if ((nib4 & 0xc) != 4)
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continue;
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break;
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default:
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abort ();
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}
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fprintf_fn (stream, "%s%s\t", dc, op->name);
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for (n = 0; n < 3 && op->arg[n] != A_END; n++)
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{
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if (n && op->arg[1] != A_END)
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fprintf_fn (stream, ",");
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switch (op->arg[n])
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{
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case DSP_REG_N:
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print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
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break;
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case DSP_REG_X:
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fprintf_fn (stream, "%s", sx_tab[(field_b >> 6) & 3]);
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break;
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case DSP_REG_Y:
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fprintf_fn (stream, "%s", sy_tab[(field_b >> 4) & 3]);
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break;
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case A_MACH:
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fprintf_fn (stream, "mach");
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break;
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case A_MACL:
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fprintf_fn (stream, "macl");
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break;
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default:
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abort ();
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}
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}
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return;
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}
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}
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/* Not found. */
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fprintf_fn (stream, ".word 0x%x", field_b);
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}
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/* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff
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(ie. the upper nibble is missing). */
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int
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print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
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{
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fprintf_ftype fprintf_fn = info->fprintf_func;
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void *stream = info->stream;
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unsigned char insn[4];
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unsigned char nibs[8];
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int status;
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bfd_vma relmask = ~(bfd_vma) 0;
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const sh_opcode_info *op;
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unsigned int target_arch;
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int allow_op32;
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switch (info->mach)
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{
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case bfd_mach_sh:
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target_arch = arch_sh1;
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/* SH coff object files lack information about the machine type, so
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we end up with bfd_mach_sh unless it was set explicitly (which
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could have happended if this is a call from gdb or the simulator.) */
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if (info->symbols
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&& bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
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target_arch = arch_sh4;
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break;
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case bfd_mach_sh5:
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#ifdef INCLUDE_SHMEDIA
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status = print_insn_sh64 (memaddr, info);
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if (status != -2)
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return status;
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#endif
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/* When we get here for sh64, it's because we want to disassemble
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SHcompact, i.e. arch_sh4. */
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target_arch = arch_sh4;
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break;
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default:
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target_arch = sh_get_arch_from_bfd_mach (info->mach);
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}
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status = info->read_memory_func (memaddr, insn, 2, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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if (info->endian == BFD_ENDIAN_LITTLE)
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{
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nibs[0] = (insn[1] >> 4) & 0xf;
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nibs[1] = insn[1] & 0xf;
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nibs[2] = (insn[0] >> 4) & 0xf;
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nibs[3] = insn[0] & 0xf;
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}
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else
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{
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nibs[0] = (insn[0] >> 4) & 0xf;
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nibs[1] = insn[0] & 0xf;
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nibs[2] = (insn[1] >> 4) & 0xf;
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nibs[3] = insn[1] & 0xf;
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}
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status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
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if (status != 0)
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allow_op32 = 0;
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else
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{
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allow_op32 = 1;
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if (info->endian == BFD_ENDIAN_LITTLE)
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{
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nibs[4] = (insn[3] >> 4) & 0xf;
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nibs[5] = insn[3] & 0xf;
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nibs[6] = (insn[2] >> 4) & 0xf;
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nibs[7] = insn[2] & 0xf;
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}
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else
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{
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nibs[4] = (insn[2] >> 4) & 0xf;
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nibs[5] = insn[2] & 0xf;
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nibs[6] = (insn[3] >> 4) & 0xf;
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nibs[7] = insn[3] & 0xf;
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}
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}
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if (nibs[0] == 0xf && (nibs[1] & 4) == 0
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&& SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
|
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{
|
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if (nibs[1] & 8)
|
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{
|
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int field_b;
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|
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status = info->read_memory_func (memaddr + 2, insn, 2, info);
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|
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if (status != 0)
|
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{
|
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info->memory_error_func (status, memaddr + 2, info);
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return -1;
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}
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|
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if (info->endian == BFD_ENDIAN_LITTLE)
|
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field_b = insn[1] << 8 | insn[0];
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else
|
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field_b = insn[0] << 8 | insn[1];
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|
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print_insn_ppi (field_b, info);
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print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
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return 4;
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}
|
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print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
|
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return 2;
|
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}
|
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for (op = sh_table; op->name; op++)
|
|
{
|
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int n;
|
|
int imm = 0;
|
|
int rn = 0;
|
|
int rm = 0;
|
|
int rb = 0;
|
|
int disp_pc;
|
|
bfd_vma disp_pc_addr = 0;
|
|
int disp = 0;
|
|
int has_disp = 0;
|
|
int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
|
|
|
|
if (!allow_op32
|
|
&& SH_MERGE_ARCH_SET (op->arch, arch_op32))
|
|
goto fail;
|
|
|
|
if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
|
|
goto fail;
|
|
for (n = 0; n < max_n; n++)
|
|
{
|
|
int i = op->nibbles[n];
|
|
|
|
if (i < 16)
|
|
{
|
|
if (nibs[n] == i)
|
|
continue;
|
|
goto fail;
|
|
}
|
|
switch (i)
|
|
{
|
|
case BRANCH_8:
|
|
imm = (nibs[2] << 4) | (nibs[3]);
|
|
if (imm & 0x80)
|
|
imm |= ~0xff;
|
|
imm = ((char) imm) * 2 + 4;
|
|
goto ok;
|
|
case BRANCH_12:
|
|
imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
|
|
if (imm & 0x800)
|
|
imm |= ~0xfff;
|
|
imm = imm * 2 + 4;
|
|
goto ok;
|
|
case IMM0_3c:
|
|
if (nibs[3] & 0x8)
|
|
goto fail;
|
|
imm = nibs[3] & 0x7;
|
|
break;
|
|
case IMM0_3s:
|
|
if (!(nibs[3] & 0x8))
|
|
goto fail;
|
|
imm = nibs[3] & 0x7;
|
|
break;
|
|
case IMM0_3Uc:
|
|
if (nibs[2] & 0x8)
|
|
goto fail;
|
|
imm = nibs[2] & 0x7;
|
|
break;
|
|
case IMM0_3Us:
|
|
if (!(nibs[2] & 0x8))
|
|
goto fail;
|
|
imm = nibs[2] & 0x7;
|
|
break;
|
|
case DISP0_12:
|
|
case DISP1_12:
|
|
disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
|
|
has_disp = 1;
|
|
goto ok;
|
|
case DISP0_12BY2:
|
|
case DISP1_12BY2:
|
|
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
|
|
relmask = ~(bfd_vma) 1;
|
|
has_disp = 1;
|
|
goto ok;
|
|
case DISP0_12BY4:
|
|
case DISP1_12BY4:
|
|
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
|
|
relmask = ~(bfd_vma) 3;
|
|
has_disp = 1;
|
|
goto ok;
|
|
case DISP0_12BY8:
|
|
case DISP1_12BY8:
|
|
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
|
|
relmask = ~(bfd_vma) 7;
|
|
has_disp = 1;
|
|
goto ok;
|
|
case IMM0_20_4:
|
|
break;
|
|
case IMM0_20:
|
|
imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
|
|
| (nibs[6] << 4) | nibs[7]);
|
|
if (imm & 0x80000)
|
|
imm -= 0x100000;
|
|
goto ok;
|
|
case IMM0_20BY8:
|
|
imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
|
|
| (nibs[6] << 4) | nibs[7]);
|
|
imm <<= 8;
|
|
if (imm & 0x8000000)
|
|
imm -= 0x10000000;
|
|
goto ok;
|
|
case IMM0_4:
|
|
case IMM1_4:
|
|
imm = nibs[3];
|
|
goto ok;
|
|
case IMM0_4BY2:
|
|
case IMM1_4BY2:
|
|
imm = nibs[3] << 1;
|
|
goto ok;
|
|
case IMM0_4BY4:
|
|
case IMM1_4BY4:
|
|
imm = nibs[3] << 2;
|
|
goto ok;
|
|
case IMM0_8:
|
|
case IMM1_8:
|
|
imm = (nibs[2] << 4) | nibs[3];
|
|
disp = imm;
|
|
has_disp = 1;
|
|
if (imm & 0x80)
|
|
imm -= 0x100;
|
|
goto ok;
|
|
case PCRELIMM_8BY2:
|
|
imm = ((nibs[2] << 4) | nibs[3]) << 1;
|
|
relmask = ~(bfd_vma) 1;
|
|
goto ok;
|
|
case PCRELIMM_8BY4:
|
|
imm = ((nibs[2] << 4) | nibs[3]) << 2;
|
|
relmask = ~(bfd_vma) 3;
|
|
goto ok;
|
|
case IMM0_8BY2:
|
|
case IMM1_8BY2:
|
|
imm = ((nibs[2] << 4) | nibs[3]) << 1;
|
|
goto ok;
|
|
case IMM0_8BY4:
|
|
case IMM1_8BY4:
|
|
imm = ((nibs[2] << 4) | nibs[3]) << 2;
|
|
goto ok;
|
|
case REG_N_D:
|
|
if ((nibs[n] & 1) != 0)
|
|
goto fail;
|
|
/* Fall through. */
|
|
case REG_N:
|
|
rn = nibs[n];
|
|
break;
|
|
case REG_M:
|
|
rm = nibs[n];
|
|
break;
|
|
case REG_N_B01:
|
|
if ((nibs[n] & 0x3) != 1 /* binary 01 */)
|
|
goto fail;
|
|
rn = (nibs[n] & 0xc) >> 2;
|
|
break;
|
|
case REG_NM:
|
|
rn = (nibs[n] & 0xc) >> 2;
|
|
rm = (nibs[n] & 0x3);
|
|
break;
|
|
case REG_B:
|
|
rb = nibs[n] & 0x07;
|
|
break;
|
|
case SDT_REG_N:
|
|
/* sh-dsp: single data transfer. */
|
|
rn = nibs[n];
|
|
if ((rn & 0xc) != 4)
|
|
goto fail;
|
|
rn = rn & 0x3;
|
|
rn |= (!(rn & 2)) << 2;
|
|
break;
|
|
case PPI:
|
|
case REPEAT:
|
|
goto fail;
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
ok:
|
|
/* sh2a has D_REG but not X_REG. We don't know the pattern
|
|
doesn't match unless we check the output args to see if they
|
|
make sense. */
|
|
if (target_arch == arch_sh2a
|
|
&& ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
|
|
|| (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
|
|
goto fail;
|
|
|
|
fprintf_fn (stream, "%s\t", op->name);
|
|
disp_pc = 0;
|
|
for (n = 0; n < 3 && op->arg[n] != A_END; n++)
|
|
{
|
|
if (n && op->arg[1] != A_END)
|
|
fprintf_fn (stream, ",");
|
|
switch (op->arg[n])
|
|
{
|
|
case A_IMM:
|
|
fprintf_fn (stream, "#%d", imm);
|
|
break;
|
|
case A_R0:
|
|
fprintf_fn (stream, "r0");
|
|
break;
|
|
case A_REG_N:
|
|
fprintf_fn (stream, "r%d", rn);
|
|
break;
|
|
case A_INC_N:
|
|
case AS_INC_N:
|
|
fprintf_fn (stream, "@r%d+", rn);
|
|
break;
|
|
case A_DEC_N:
|
|
case AS_DEC_N:
|
|
fprintf_fn (stream, "@-r%d", rn);
|
|
break;
|
|
case A_IND_N:
|
|
case AS_IND_N:
|
|
fprintf_fn (stream, "@r%d", rn);
|
|
break;
|
|
case A_DISP_REG_N:
|
|
fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
|
|
break;
|
|
case AS_PMOD_N:
|
|
fprintf_fn (stream, "@r%d+r8", rn);
|
|
break;
|
|
case A_REG_M:
|
|
fprintf_fn (stream, "r%d", rm);
|
|
break;
|
|
case A_INC_M:
|
|
fprintf_fn (stream, "@r%d+", rm);
|
|
break;
|
|
case A_DEC_M:
|
|
fprintf_fn (stream, "@-r%d", rm);
|
|
break;
|
|
case A_IND_M:
|
|
fprintf_fn (stream, "@r%d", rm);
|
|
break;
|
|
case A_DISP_REG_M:
|
|
fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
|
|
break;
|
|
case A_REG_B:
|
|
fprintf_fn (stream, "r%d_bank", rb);
|
|
break;
|
|
case A_DISP_PC:
|
|
disp_pc = 1;
|
|
disp_pc_addr = imm + 4 + (memaddr & relmask);
|
|
(*info->print_address_func) (disp_pc_addr, info);
|
|
break;
|
|
case A_IND_R0_REG_N:
|
|
fprintf_fn (stream, "@(r0,r%d)", rn);
|
|
break;
|
|
case A_IND_R0_REG_M:
|
|
fprintf_fn (stream, "@(r0,r%d)", rm);
|
|
break;
|
|
case A_DISP_GBR:
|
|
fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
|
|
break;
|
|
case A_TBR:
|
|
fprintf_fn (stream, "tbr");
|
|
break;
|
|
case A_DISP2_TBR:
|
|
fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
|
|
break;
|
|
case A_INC_R15:
|
|
fprintf_fn (stream, "@r15+");
|
|
break;
|
|
case A_DEC_R15:
|
|
fprintf_fn (stream, "@-r15");
|
|
break;
|
|
case A_R0_GBR:
|
|
fprintf_fn (stream, "@(r0,gbr)");
|
|
break;
|
|
case A_BDISP12:
|
|
case A_BDISP8:
|
|
(*info->print_address_func) (imm + memaddr, info);
|
|
break;
|
|
case A_SR:
|
|
fprintf_fn (stream, "sr");
|
|
break;
|
|
case A_GBR:
|
|
fprintf_fn (stream, "gbr");
|
|
break;
|
|
case A_VBR:
|
|
fprintf_fn (stream, "vbr");
|
|
break;
|
|
case A_DSR:
|
|
fprintf_fn (stream, "dsr");
|
|
break;
|
|
case A_MOD:
|
|
fprintf_fn (stream, "mod");
|
|
break;
|
|
case A_RE:
|
|
fprintf_fn (stream, "re");
|
|
break;
|
|
case A_RS:
|
|
fprintf_fn (stream, "rs");
|
|
break;
|
|
case A_A0:
|
|
fprintf_fn (stream, "a0");
|
|
break;
|
|
case A_X0:
|
|
fprintf_fn (stream, "x0");
|
|
break;
|
|
case A_X1:
|
|
fprintf_fn (stream, "x1");
|
|
break;
|
|
case A_Y0:
|
|
fprintf_fn (stream, "y0");
|
|
break;
|
|
case A_Y1:
|
|
fprintf_fn (stream, "y1");
|
|
break;
|
|
case DSP_REG_M:
|
|
print_dsp_reg (rm, fprintf_fn, stream);
|
|
break;
|
|
case A_SSR:
|
|
fprintf_fn (stream, "ssr");
|
|
break;
|
|
case A_SPC:
|
|
fprintf_fn (stream, "spc");
|
|
break;
|
|
case A_MACH:
|
|
fprintf_fn (stream, "mach");
|
|
break;
|
|
case A_MACL:
|
|
fprintf_fn (stream, "macl");
|
|
break;
|
|
case A_PR:
|
|
fprintf_fn (stream, "pr");
|
|
break;
|
|
case A_SGR:
|
|
fprintf_fn (stream, "sgr");
|
|
break;
|
|
case A_DBR:
|
|
fprintf_fn (stream, "dbr");
|
|
break;
|
|
case F_REG_N:
|
|
fprintf_fn (stream, "fr%d", rn);
|
|
break;
|
|
case F_REG_M:
|
|
fprintf_fn (stream, "fr%d", rm);
|
|
break;
|
|
case DX_REG_N:
|
|
if (rn & 1)
|
|
{
|
|
fprintf_fn (stream, "xd%d", rn & ~1);
|
|
break;
|
|
}
|
|
case D_REG_N:
|
|
fprintf_fn (stream, "dr%d", rn);
|
|
break;
|
|
case DX_REG_M:
|
|
if (rm & 1)
|
|
{
|
|
fprintf_fn (stream, "xd%d", rm & ~1);
|
|
break;
|
|
}
|
|
case D_REG_M:
|
|
fprintf_fn (stream, "dr%d", rm);
|
|
break;
|
|
case FPSCR_M:
|
|
case FPSCR_N:
|
|
fprintf_fn (stream, "fpscr");
|
|
break;
|
|
case FPUL_M:
|
|
case FPUL_N:
|
|
fprintf_fn (stream, "fpul");
|
|
break;
|
|
case F_FR0:
|
|
fprintf_fn (stream, "fr0");
|
|
break;
|
|
case V_REG_N:
|
|
fprintf_fn (stream, "fv%d", rn * 4);
|
|
break;
|
|
case V_REG_M:
|
|
fprintf_fn (stream, "fv%d", rm * 4);
|
|
break;
|
|
case XMTRX_M4:
|
|
fprintf_fn (stream, "xmtrx");
|
|
break;
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
/* This code prints instructions in delay slots on the same line
|
|
as the instruction which needs the delay slots. This can be
|
|
confusing, since other disassembler don't work this way, and
|
|
it means that the instructions are not all in a line. So I
|
|
disabled it. Ian. */
|
|
if (!(info->flags & 1)
|
|
&& (op->name[0] == 'j'
|
|
|| (op->name[0] == 'b'
|
|
&& (op->name[1] == 'r'
|
|
|| op->name[1] == 's'))
|
|
|| (op->name[0] == 'r' && op->name[1] == 't')
|
|
|| (op->name[0] == 'b' && op->name[2] == '.')))
|
|
{
|
|
info->flags |= 1;
|
|
fprintf_fn (stream, "\t(slot ");
|
|
print_insn_sh (memaddr + 2, info);
|
|
info->flags &= ~1;
|
|
fprintf_fn (stream, ")");
|
|
return 4;
|
|
}
|
|
#endif
|
|
|
|
if (disp_pc && strcmp (op->name, "mova") != 0)
|
|
{
|
|
int size;
|
|
bfd_byte bytes[4];
|
|
|
|
if (relmask == ~(bfd_vma) 1)
|
|
size = 2;
|
|
else
|
|
size = 4;
|
|
status = info->read_memory_func (disp_pc_addr, bytes, size, info);
|
|
if (status == 0)
|
|
{
|
|
unsigned int val;
|
|
|
|
if (size == 2)
|
|
{
|
|
if (info->endian == BFD_ENDIAN_LITTLE)
|
|
val = bfd_getl16 (bytes);
|
|
else
|
|
val = bfd_getb16 (bytes);
|
|
}
|
|
else
|
|
{
|
|
if (info->endian == BFD_ENDIAN_LITTLE)
|
|
val = bfd_getl32 (bytes);
|
|
else
|
|
val = bfd_getb32 (bytes);
|
|
}
|
|
if ((*info->symbol_at_address_func) (val, info))
|
|
{
|
|
fprintf_fn (stream, "\t! ");
|
|
(*info->print_address_func) (val, info);
|
|
}
|
|
else
|
|
fprintf_fn (stream, "\t! %x", val);
|
|
}
|
|
}
|
|
|
|
return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
|
|
fail:
|
|
;
|
|
|
|
}
|
|
fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
|
|
return 2;
|
|
}
|