729 lines
28 KiB
C
729 lines
28 KiB
C
/* MIPS Simulator definition.
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Copyright (C) 1997 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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/* This simulator doesn't cache the Current Instruction Address */
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/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
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/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
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#define SIM_HAVE_BIENDIAN
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/* hobble some common features for moment */
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#define WITH_WATCHPOINTS 1
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#define WITH_MODULO_MEMORY 1
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#include "sim-basics.h"
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typedef address_word sim_cia;
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#if (WITH_IGEN)
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/* Get the number of instructions. FIXME: must be a more elegant way
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of doing this. */
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#include "itable.h"
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#define MAX_INSNS (nr_itable_entries)
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#define INSN_NAME(i) itable[(i)].name
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#endif
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#include "sim-base.h"
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/* Depreciated macros and types for manipulating 64bit values. Use
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../common/sim-bits.h and ../common/sim-endian.h macros instead. */
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typedef signed64 word64;
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typedef unsigned64 uword64;
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#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
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#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
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#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
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#define SET64HI(t) (((uword64)(t))<<32)
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#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
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#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
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/* Sign-extend the given value (e) as a value (b) bits long. We cannot
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assume the HI32bits of the operand are zero, so we must perform a
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mask to ensure we can use the simple subtraction to sign-extend. */
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#define SIGNEXTEND(e,b) \
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((unsigned_word) \
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(((e) & ((uword64) 1 << ((b) - 1))) \
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? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
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: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
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/* Check if a value will fit within a halfword: */
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#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
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/* Floating-point operations: */
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#include "sim-fpu.h"
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/* FPU registers must be one of the following types. All other values
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are reserved (and undefined). */
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typedef enum {
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fmt_single = 0,
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fmt_double = 1,
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fmt_word = 4,
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fmt_long = 5,
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/* The following are well outside the normal acceptable format
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range, and are used in the register status vector. */
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fmt_unknown = 0x10000000,
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fmt_uninterpreted = 0x20000000,
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fmt_uninterpreted_32 = 0x40000000,
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fmt_uninterpreted_64 = 0x80000000,
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} FP_formats;
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unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
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#define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
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void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
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#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
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int NaN PARAMS ((unsigned64 op, FP_formats fmt));
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int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
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int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
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#define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
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/* Macro to update FPSR condition-code field. This is complicated by
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the fact that there is a hole in the index range of the bits within
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the FCSR register. Also, the number of bits visible depends on the
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MIPS ISA version being supported. */
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#define SETFCC(cc,v) {\
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int bit = ((cc == 0) ? 23 : (24 + (cc)));\
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FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
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}
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#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
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/* This should be the COC1 value at the start of the preceding
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instruction: */
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#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
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#if 1
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#define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
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#else
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/* They depend on the CPU being simulated */
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#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
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#endif
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/* Standard FCRS bits: */
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#define IR (0) /* Inexact Result */
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#define UF (1) /* UnderFlow */
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#define OF (2) /* OverFlow */
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#define DZ (3) /* Division by Zero */
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#define IO (4) /* Invalid Operation */
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#define UO (5) /* Unimplemented Operation */
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/* Get masks for individual flags: */
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#if 1 /* SAFE version */
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#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
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#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
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#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
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#else
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#define FP_FLAGS(b) (1 << ((b) + 2))
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#define FP_ENABLE(b) (1 << ((b) + 7))
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#define FP_CAUSE(b) (1 << ((b) + 12))
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#endif
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#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
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#define FP_MASK_RM (0x3)
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#define FP_SH_RM (0)
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#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
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#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
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#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
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#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
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#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
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/* Integer ALU operations: */
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#include "sim-alu.h"
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#define ALU32_END(ANS) \
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if (ALU32_HAD_OVERFLOW) \
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SignalExceptionIntegerOverflow (); \
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(ANS) = ALU32_OVERFLOW_RESULT
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#define ALU64_END(ANS) \
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if (ALU64_HAD_OVERFLOW) \
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SignalExceptionIntegerOverflow (); \
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(ANS) = ALU64_OVERFLOW_RESULT;
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/* start-sanitize-r5900 */
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#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
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#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
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#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
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#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
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#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
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#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
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#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
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#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
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/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
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T - type of the sub part
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TC - # of T's in the mips part of the "register"
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I - index (from 0) of desired sub part
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A - low part of "register"
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A1 - high part of register
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*/
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#define SUB_REG_FETCH(T,TC,A,A1,I) \
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(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
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+ (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
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? ((TC) - 1 - (I) % (TC)) \
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: ((I) % (TC)) \
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) \
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) \
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)
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/*
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GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
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where <type> has two letters:
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1 is S=signed or U=unsigned
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2 is B=byte H=halfword W=word D=doubleword
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*/
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#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
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#define GPR_SB(R,I) SUB_REG_SB(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_SH(R,I) SUB_REG_SH(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_SW(R,I) SUB_REG_SW(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_SD(R,I) SUB_REG_SD(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_UB(R,I) SUB_REG_UB(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_UH(R,I) SUB_REG_UH(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_UW(R,I) SUB_REG_UW(®ISTERS[R], ®ISTERS1[R], I)
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#define GPR_UD(R,I) SUB_REG_UD(®ISTERS[R], ®ISTERS1[R], I)
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#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
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#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
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#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
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#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
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#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
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#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
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#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
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#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
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#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
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#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
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#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
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#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
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#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
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#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
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#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
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#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
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#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
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#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
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#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
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#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
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#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
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#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
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#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
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#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
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#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
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#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
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#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
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#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
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#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
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#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
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#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
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#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
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/* end-sanitize-r5900 */
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struct _sim_cpu {
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/* The following are internal simulator state variables: */
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#define CPU_CIA(CPU) (PC)
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address_word dspc; /* delay-slot PC */
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#define DSPC ((STATE_CPU (sd,0))->dspc)
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/* Issue a delay slot instruction immediatly by re-calling
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idecode_issue */
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#define DELAY_SLOT(TARGET) \
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do { \
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address_word target = (TARGET); \
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instruction_word delay_insn; \
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sim_events_slip (sd, 1); \
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CIA = CIA + 4; \
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STATE |= simDELAYSLOT; \
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delay_insn = IMEM (CIA); \
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idecode_issue (sd, delay_insn, (CIA)); \
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STATE &= ~simDELAYSLOT; \
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NIA = target; \
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} while (0)
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#define NULLIFY_NEXT_INSTRUCTION() \
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do { \
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sim_events_slip (sd, 1); \
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dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
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NIA = CIA + 8; \
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} while (0)
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/* State of the simulator */
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unsigned int state;
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unsigned int dsstate;
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#define STATE ((STATE_CPU (sd,0))->state)
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#define DSSTATE ((STATE_CPU (sd,0))->dsstate)
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/* Flags in the "state" variable: */
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#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
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#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
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#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
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#define simPCOC0 (1 << 17) /* COC[1] from current */
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#define simPCOC1 (1 << 18) /* COC[1] from previous */
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#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
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#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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#define ENGINE_ISSUE_PREFIX_HOOK() \
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{ \
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/* Set previous flag, depending on current: */ \
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if (STATE & simPCOC0) \
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STATE |= simPCOC1; \
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else \
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STATE &= ~simPCOC1; \
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/* and update the current value: */ \
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if (GETFCC(0)) \
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STATE |= simPCOC0; \
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else \
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STATE &= ~simPCOC0; \
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}
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/* This is nasty, since we have to rely on matching the register
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numbers used by GDB. Unfortunately, depending on the MIPS target
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GDB uses different register numbers. We cannot just include the
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relevant "gdb/tm.h" link, since GDB may not be configured before
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the sim world, and also the GDB header file requires too much other
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state. */
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#ifndef TM_MIPS_H
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#define LAST_EMBED_REGNUM (89)
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#define NUM_REGS (LAST_EMBED_REGNUM + 1)
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/* start-sanitize-r5900 */
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#undef NUM_REGS
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#define NUM_REGS (128)
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/* end-sanitize-r5900 */
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#endif
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/* To keep this default simulator simple, and fast, we use a direct
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vector of registers. The internal simulator engine then uses
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manifests to access the correct slot. */
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unsigned_word registers[LAST_EMBED_REGNUM + 1];
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int register_widths[NUM_REGS];
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#define REGISTERS ((STATE_CPU (sd,0))->registers)
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#define GPR (®ISTERS[0])
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#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
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#define FGRIDX (38)
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#define FGR (®ISTERS[FGRIDX])
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#define LO (REGISTERS[33])
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#define HI (REGISTERS[34])
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#define PC (REGISTERS[37])
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#define CAUSE (REGISTERS[36])
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#define SRIDX (32)
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#define SR (REGISTERS[SRIDX]) /* CPU status register */
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#define FCR0IDX (71)
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#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
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#define FCR31IDX (70)
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#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
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#define FCSR (FCR31)
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#define Debug (REGISTERS[86])
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#define DEPC (REGISTERS[87])
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#define EPC (REGISTERS[88])
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#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
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unsigned_word c0_config_reg;
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#define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
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/* The following are pseudonyms for standard registers */
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#define ZERO (REGISTERS[0])
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#define V0 (REGISTERS[2])
|
|
#define A0 (REGISTERS[4])
|
|
#define A1 (REGISTERS[5])
|
|
#define A2 (REGISTERS[6])
|
|
#define A3 (REGISTERS[7])
|
|
#define SP (REGISTERS[29])
|
|
#define RA (REGISTERS[31])
|
|
|
|
/* Keep the current format state for each register: */
|
|
FP_formats fpr_state[32];
|
|
#define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
|
|
|
|
|
|
/* Slots for delayed register updates. For the moment we just have a
|
|
fixed number of slots (rather than a more generic, dynamic
|
|
system). This keeps the simulator fast. However, we only allow
|
|
for the register update to be delayed for a single instruction
|
|
cycle. */
|
|
#define PSLOTS (5) /* Maximum number of instruction cycles */
|
|
int pending_in;
|
|
int pending_out;
|
|
int pending_total;
|
|
int pending_slot_count[PSLOTS];
|
|
int pending_slot_reg[PSLOTS];
|
|
unsigned_word pending_slot_value[PSLOTS];
|
|
#define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
|
|
#define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
|
|
#define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
|
|
#define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
|
|
#define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
|
|
#define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
|
|
|
|
/* The following are not used for MIPS IV onwards: */
|
|
#define PENDING_FILL(r,v) {\
|
|
/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
|
|
if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
|
|
sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
|
|
PENDING_SLOT_COUNT[PENDING_IN] = 2;\
|
|
PENDING_SLOT_REG[PENDING_IN] = (r);\
|
|
PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
|
|
/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
|
|
PENDING_TOTAL++;\
|
|
PENDING_IN++;\
|
|
if (PENDING_IN == PSLOTS)\
|
|
PENDING_IN = 0;\
|
|
/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
|
|
}
|
|
|
|
|
|
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
|
|
read-write instructions. It is set when a linked load occurs. It
|
|
is tested and cleared by the conditional store. It is cleared
|
|
(during other CPU operations) when a store to the location would
|
|
no longer be atomic. In particular, it is cleared by exception
|
|
return instructions. */
|
|
int llbit;
|
|
#define LLBIT ((STATE_CPU (sd, 0))->llbit)
|
|
|
|
|
|
/* The HIACCESS and LOACCESS counts are used to ensure that
|
|
corruptions caused by using the HI or LO register to close to a
|
|
following operation are spotted. */
|
|
|
|
int hiaccess;
|
|
int loaccess;
|
|
#define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
|
|
#define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
|
|
/* start-sanitize-r5900 */
|
|
int hi1access;
|
|
int lo1access;
|
|
#define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
|
|
#define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
|
|
/* end-sanitize-r5900 */
|
|
#if 1
|
|
/* The 4300 and a few other processors have interlocks on hi/lo
|
|
register reads, and hence do not have this problem. To avoid
|
|
spurious warnings, we just disable this always. */
|
|
#define CHECKHILO(s)
|
|
#else
|
|
unsigned_word HLPC;
|
|
/* If either of the preceding two instructions have accessed the HI
|
|
or LO registers, then the values they see should be
|
|
undefined. However, to keep the simulator world simple, we just
|
|
let them use the value read and raise a warning to notify the
|
|
user: */
|
|
#define CHECKHILO(s) {\
|
|
if ((HIACCESS != 0) || (LOACCESS != 0)) \
|
|
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
|
|
}
|
|
/* start-sanitize-r5900 */
|
|
#undef CHECKHILO
|
|
#define CHECKHILO(s) {\
|
|
if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
|
|
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
|
|
}
|
|
/* end-sanitize-r5900 */
|
|
#endif
|
|
|
|
|
|
/* start-sanitize-r5900 */
|
|
/* The R5900 has 128 bit registers, but the hi 64 bits are only
|
|
touched by multimedia (MMI) instructions. The normal mips
|
|
instructions just use the lower 64 bits. To avoid changing the
|
|
older parts of the simulator to handle this weirdness, the high
|
|
64 bits of each register are kept in a separate array
|
|
(registers1). The high 64 bits of any register are by convention
|
|
refered by adding a '1' to the end of the normal register's name.
|
|
So LO still refers to the low 64 bits of the LO register, LO1
|
|
refers to the high 64 bits of that same register. */
|
|
|
|
signed_word registers1[LAST_EMBED_REGNUM + 1];
|
|
#define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
|
|
#define GPR1 (®ISTERS1[0])
|
|
#define LO1 (REGISTERS1[32])
|
|
#define HI1 (REGISTERS1[33])
|
|
#define REGISTER_SA (124)
|
|
|
|
unsigned_word sa; /* the shift amount register */
|
|
#define SA ((STATE_CPU (sd, 0))->sa)
|
|
|
|
/* end-sanitize-r5900 */
|
|
/* start-sanitize-vr5400 */
|
|
|
|
/* The MDMX ISA has a very very large accumulator */
|
|
unsigned8 acc[3 * 8];
|
|
/* end-sanitize-vr5400 */
|
|
|
|
sim_cpu_base base;
|
|
};
|
|
|
|
|
|
/* MIPS specific simulator watch config */
|
|
|
|
void watch_options_install PARAMS ((SIM_DESC sd));
|
|
|
|
struct swatch {
|
|
sim_event *pc;
|
|
sim_event *clock;
|
|
sim_event *cycles;
|
|
};
|
|
|
|
|
|
/* FIXME: At present much of the simulator is still static */
|
|
struct sim_state {
|
|
|
|
struct swatch watch;
|
|
|
|
sim_cpu cpu[1];
|
|
#if (WITH_SMP)
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
|
|
#else
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
|
|
#endif
|
|
|
|
sim_state_base base;
|
|
};
|
|
|
|
|
|
|
|
/* Status information: */
|
|
|
|
/* TODO : these should be the bitmasks for these bits within the
|
|
status register. At the moment the following are VR4300
|
|
bit-positions: */
|
|
#define status_KSU_mask (0x3) /* mask for KSU bits */
|
|
#define status_KSU_shift (3) /* shift for field */
|
|
#define ksu_kernel (0x0)
|
|
#define ksu_supervisor (0x1)
|
|
#define ksu_user (0x2)
|
|
#define ksu_unknown (0x3)
|
|
|
|
#define status_IE (1 << 0) /* Interrupt enable */
|
|
#define status_EXL (1 << 1) /* Exception level */
|
|
#define status_RE (1 << 25) /* Reverse Endian in user mode */
|
|
#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
|
|
#define status_SR (1 << 20) /* soft reset or NMI */
|
|
#define status_BEV (1 << 22) /* Location of general exception vectors */
|
|
#define status_TS (1 << 21) /* TLB shutdown has occurred */
|
|
#define status_ERL (1 << 2) /* Error level */
|
|
#define status_RP (1 << 27) /* Reduced Power mode */
|
|
|
|
#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
|
|
|
|
/* NOTE: We keep the following status flags as bit values (1 for true,
|
|
0 for false). This allows them to be used in binary boolean
|
|
operations without worrying about what exactly the non-zero true
|
|
value is. */
|
|
|
|
/* UserMode */
|
|
#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
|
|
|
|
/* BigEndianMem */
|
|
/* Hardware configuration. Affects endianness of LoadMemory and
|
|
StoreMemory and the endianness of Kernel and Supervisor mode
|
|
execution. The value is 0 for little-endian; 1 for big-endian. */
|
|
#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
|
|
/*(state & simBE) ? 1 : 0)*/
|
|
|
|
/* ReverseEndian */
|
|
/* This mode is selected if in User mode with the RE bit being set in
|
|
SR (Status Register). It reverses the endianness of load and store
|
|
instructions. */
|
|
#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
|
|
|
|
/* BigEndianCPU */
|
|
/* The endianness for load and store instructions (0=little;1=big). In
|
|
User mode this endianness may be switched by setting the state_RE
|
|
bit in the SR register. Thus, BigEndianCPU may be computed as
|
|
(BigEndianMem EOR ReverseEndian). */
|
|
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
|
|
|
|
|
|
|
|
/* Exceptions: */
|
|
|
|
/* NOTE: These numbers depend on the processor architecture being
|
|
simulated: */
|
|
#define Interrupt (0)
|
|
#define TLBModification (1)
|
|
#define TLBLoad (2)
|
|
#define TLBStore (3)
|
|
#define AddressLoad (4)
|
|
#define AddressStore (5)
|
|
#define InstructionFetch (6)
|
|
#define DataReference (7)
|
|
#define SystemCall (8)
|
|
#define BreakPoint (9)
|
|
#define ReservedInstruction (10)
|
|
#define CoProcessorUnusable (11)
|
|
#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
|
|
#define Trap (13)
|
|
#define FPE (15)
|
|
#define DebugBreakPoint (16)
|
|
#define Watch (23)
|
|
|
|
/* The following exception code is actually private to the simulator
|
|
world. It is *NOT* a processor feature, and is used to signal
|
|
run-time errors in the simulator. */
|
|
#define SimulatorFault (0xFFFFFFFF)
|
|
|
|
void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
|
|
#define SignalException(exc,instruction) signal_exception (sd, cia, (exc), (instruction))
|
|
#define SignalExceptionInterrupt() signal_exception (sd, NULL_CIA, Interrupt)
|
|
#define SignalExceptionInstructionFetch() signal_exception (sd, cia, InstructionFetch)
|
|
#define SignalExceptionAddressStore() signal_exception (sd, cia, AddressStore)
|
|
#define SignalExceptionAddressLoad() signal_exception (sd, cia, AddressLoad)
|
|
#define SignalExceptionSimulatorFault(buf) signal_exception (sd, cia, SimulatorFault, buf)
|
|
#define SignalExceptionFPE() signal_exception (sd, cia, FPE)
|
|
#define SignalExceptionIntegerOverflow() signal_exception (sd, cia, IntegerOverflow)
|
|
#define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
|
|
|
|
|
|
/* Co-processor accesses */
|
|
|
|
void cop_lw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
|
|
void cop_ld PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
|
|
unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
|
|
uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
|
|
|
|
#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
|
|
#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
|
|
#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
|
|
#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
|
|
|
|
void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
|
|
#define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
|
|
|
|
|
|
|
|
/* Memory accesses */
|
|
|
|
/* The following are generic to all versions of the MIPS architecture
|
|
to date: */
|
|
|
|
/* Memory Access Types (for CCA): */
|
|
#define Uncached (0)
|
|
#define CachedNoncoherent (1)
|
|
#define CachedCoherent (2)
|
|
#define Cached (3)
|
|
|
|
#define isINSTRUCTION (1 == 0) /* FALSE */
|
|
#define isDATA (1 == 1) /* TRUE */
|
|
#define isLOAD (1 == 0) /* FALSE */
|
|
#define isSTORE (1 == 1) /* TRUE */
|
|
#define isREAL (1 == 0) /* FALSE */
|
|
#define isRAW (1 == 1) /* TRUE */
|
|
/* The parameter HOST (isTARGET / isHOST) is ignored */
|
|
#define isTARGET (1 == 0) /* FALSE */
|
|
/* #define isHOST (1 == 1) TRUE */
|
|
|
|
/* The "AccessLength" specifications for Loads and Stores. NOTE: This
|
|
is the number of bytes minus 1. */
|
|
#define AccessLength_BYTE (0)
|
|
#define AccessLength_HALFWORD (1)
|
|
#define AccessLength_TRIPLEBYTE (2)
|
|
#define AccessLength_WORD (3)
|
|
#define AccessLength_QUINTIBYTE (4)
|
|
#define AccessLength_SEXTIBYTE (5)
|
|
#define AccessLength_SEPTIBYTE (6)
|
|
#define AccessLength_DOUBLEWORD (7)
|
|
#define AccessLength_QUADWORD (15)
|
|
|
|
int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
|
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
|
address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
|
|
|
|
void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
|
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
|
load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
|
|
|
|
void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
|
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
|
store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
|
|
|
|
void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
|
#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
|
|
|
|
void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
|
|
#define SyncOperation(stype) sync_operation (sd, cia, (stype))
|
|
|
|
void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
|
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
|
|
|
|
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
|
|
#define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
|
|
|
|
void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
|
FILE *tracefh;
|
|
|
|
#endif
|