8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
606 lines
15 KiB
C
606 lines
15 KiB
C
/* The common simulator framework for GDB, the GNU Debugger.
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Copyright 2002-2013 Free Software Foundation, Inc.
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Contributed by Andrew Cagney and Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "hw-main.h"
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#include "sim-io.h"
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/* NOTE: pal is naughty and grubs around looking at things outside of
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its immediate domain */
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#include "hw-tree.h"
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#ifdef HAVE_STRING_H
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#include <string.h>
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#else
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#ifdef HAVE_STRINGS_H
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#include <strings.h>
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#endif
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#endif
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#ifdef HAVE_UNISTD_H
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#include <unistd.h>
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#endif
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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/* DEVICE
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pal - glue logic device containing assorted junk
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DESCRIPTION
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Typical hardware dependant hack. This device allows the firmware
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to gain access to all the things the firmware needs (but the OS
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doesn't).
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The pal contains the following registers:
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|0 reset register (write, 8bit)
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|4 processor id register (read, 8bit)
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|8 interrupt register (8 - port, 9 - level) (write, 16bit)
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|12 processor count register (read, 8bit)
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|16 tty input fifo register (read, 8bit)
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|20 tty input status register (read, 8bit)
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|24 tty output fifo register (write, 8bit)
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|28 tty output status register (read, 8bit)
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|32 countdown register (read/write, 32bit, big-endian)
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|36 countdown value register (read, 32bit, big-endian)
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|40 timer register (read/write, 32bit, big-endian)
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|44 timer value register (read, 32bit, big-endian)
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RESET (write): halts the simulator. The value written to the
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register is used as an exit status.
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PROCESSOR ID (read): returns the processor identifier (0 .. N-1) of
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the processor performing the read.
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INTERRUPT (write): This register must be written using a two byte
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store. The low byte specifies a port and the upper byte specifies
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the a level. LEVEL is driven on the specified port. By
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convention, the pal's interrupt ports (int0, int1, ...) are wired
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up to the corresponding processor's level sensative external
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interrupt pin. Eg: A two byte write to address 8 of 0x0102
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(big-endian) will result in processor 2's external interrupt pin
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being asserted.
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PROCESSOR COUNT (read): returns the total number of processors
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active in the current simulation.
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TTY INPUT FIFO (read): if the TTY input status register indicates a
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character is available by being nonzero, returns the next available
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character from the pal's tty input port.
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TTY OUTPUT FIFO (write): if the TTY output status register
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indicates the output fifo is not full by being nonzero, outputs the
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character written to the tty's output port.
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COUNDOWN (read/write): The countdown registers provide a
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non-repeating timed interrupt source. Writing a 32 bit big-endian
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zero value to this register clears the countdown timer. Writing a
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non-zero 32 bit big-endian value to this register sets the
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countdown timer to expire in VALUE ticks (ticks is target
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dependant). Reading the countdown register returns the last value
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writen.
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COUNTDOWN VALUE (read): Reading this 32 bit big-endian register
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returns the number of ticks remaining until the countdown timer
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expires.
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TIMER (read/write): The timer registers provide a periodic timed
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interrupt source. Writing a 32 bit big-endian zero value to this
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register clears the periodic timer. Writing a 32 bit non-zero
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value to this register sets the periodic timer to triger every
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VALUE ticks (ticks is target dependant). Reading the timer
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register returns the last value written.
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TIMER VALUE (read): Reading this 32 bit big-endian register returns
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the number of ticks until the next periodic interrupt.
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PROPERTIES
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reg = <address> <size> (required)
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Specify the address (within the parent bus) that this device is to
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be located.
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poll? = <boolean>
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If present and true, indicates that the device should poll its
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input.
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PORTS
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int[0..NR_PROCESSORS] (output)
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Driven as a result of a write to the interrupt-port /
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interrupt-level register pair.
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countdown
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Driven whenever the countdown counter reaches zero.
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timer
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Driven whenever the timer counter reaches zero.
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BUGS
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At present the common simulator framework does not support input
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polling.
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*/
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enum {
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hw_pal_reset_register = 0x0,
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hw_pal_cpu_nr_register = 0x4,
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hw_pal_int_register = 0x8,
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hw_pal_nr_cpu_register = 0xa,
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hw_pal_read_fifo = 0x10,
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hw_pal_read_status = 0x14,
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hw_pal_write_fifo = 0x18,
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hw_pal_write_status = 0x1a,
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hw_pal_countdown = 0x20,
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hw_pal_countdown_value = 0x24,
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hw_pal_timer = 0x28,
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hw_pal_timer_value = 0x2c,
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hw_pal_address_mask = 0x3f,
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};
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typedef struct _hw_pal_console_buffer {
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char buffer;
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int status;
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} hw_pal_console_buffer;
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typedef struct _hw_pal_counter {
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struct hw_event *handler;
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signed64 start;
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unsigned32 delta;
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int periodic_p;
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} hw_pal_counter;
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typedef struct _hw_pal_device {
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hw_pal_console_buffer input;
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hw_pal_console_buffer output;
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hw_pal_counter countdown;
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hw_pal_counter timer;
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struct hw *disk;
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do_hw_poll_read_method *reader;
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} hw_pal_device;
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enum {
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COUNTDOWN_PORT,
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TIMER_PORT,
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INT_PORT,
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};
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static const struct hw_port_descriptor hw_pal_ports[] = {
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{ "countdown", COUNTDOWN_PORT, 0, output_port, },
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{ "timer", TIMER_PORT, 0, output_port, },
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{ "int", INT_PORT, MAX_NR_PROCESSORS, output_port, },
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{ NULL, 0, 0, 0 }
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};
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/* countdown and simple timer */
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static void
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do_counter_event (struct hw *me,
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void *data)
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{
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hw_pal_counter *counter = (hw_pal_counter *) data;
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if (counter->periodic_p)
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{
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HW_TRACE ((me, "timer expired"));
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counter->start = hw_event_queue_time (me);
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hw_port_event (me, TIMER_PORT, 1);
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hw_event_queue_schedule (me, counter->delta, do_counter_event, counter);
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}
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else
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{
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HW_TRACE ((me, "countdown expired"));
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counter->delta = 0;
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hw_port_event (me, COUNTDOWN_PORT, 1);
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}
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}
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static void
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do_counter_read (struct hw *me,
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hw_pal_device *pal,
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const char *reg,
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hw_pal_counter *counter,
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unsigned32 *word,
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unsigned nr_bytes)
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{
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unsigned32 val;
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if (nr_bytes != 4)
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hw_abort (me, "%s - bad read size must be 4 bytes", reg);
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val = counter->delta;
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HW_TRACE ((me, "read - %s %ld", reg, (long) val));
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*word = H2BE_4 (val);
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}
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static void
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do_counter_value (struct hw *me,
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hw_pal_device *pal,
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const char *reg,
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hw_pal_counter *counter,
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unsigned32 *word,
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unsigned nr_bytes)
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{
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unsigned32 val;
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if (nr_bytes != 4)
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hw_abort (me, "%s - bad read size must be 4 bytes", reg);
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if (counter->delta != 0)
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val = (counter->start + counter->delta
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- hw_event_queue_time (me));
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else
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val = 0;
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HW_TRACE ((me, "read - %s %ld", reg, (long) val));
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*word = H2BE_4 (val);
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}
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static void
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do_counter_write (struct hw *me,
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hw_pal_device *pal,
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const char *reg,
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hw_pal_counter *counter,
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const unsigned32 *word,
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unsigned nr_bytes)
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{
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if (nr_bytes != 4)
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hw_abort (me, "%s - bad write size must be 4 bytes", reg);
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if (counter->handler != NULL)
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{
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hw_event_queue_deschedule (me, counter->handler);
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counter->handler = NULL;
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}
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counter->delta = BE2H_4 (*word);
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counter->start = hw_event_queue_time (me);
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HW_TRACE ((me, "write - %s %ld", reg, (long) counter->delta));
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if (counter->delta > 0)
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hw_event_queue_schedule (me, counter->delta, do_counter_event, counter);
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}
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/* check the console for an available character */
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static void
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scan_hw_pal (struct hw *me)
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{
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hw_pal_device *hw_pal = (hw_pal_device *)hw_data (me);
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char c;
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int count;
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count = do_hw_poll_read (me, hw_pal->reader, 0/*STDIN*/, &c, sizeof (c));
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switch (count)
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{
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case HW_IO_NOT_READY:
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case HW_IO_EOF:
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hw_pal->input.buffer = 0;
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hw_pal->input.status = 0;
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break;
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default:
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hw_pal->input.buffer = c;
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hw_pal->input.status = 1;
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}
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}
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/* write the character to the hw_pal */
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static void
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write_hw_pal (struct hw *me,
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char val)
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{
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hw_pal_device *hw_pal = (hw_pal_device *) hw_data (me);
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sim_io_write_stdout (hw_system (me), &val, 1);
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hw_pal->output.buffer = val;
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hw_pal->output.status = 1;
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}
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/* Reads/writes */
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static unsigned
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hw_pal_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word addr,
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unsigned nr_bytes)
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{
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hw_pal_device *hw_pal = (hw_pal_device *) hw_data (me);
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unsigned_1 *byte = (unsigned_1 *) dest;
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memset (dest, 0, nr_bytes);
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switch (addr & hw_pal_address_mask)
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{
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case hw_pal_cpu_nr_register:
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#ifdef CPU_INDEX
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*byte = CPU_INDEX (hw_system_cpu (me));
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#else
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*byte = 0;
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#endif
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HW_TRACE ((me, "read - cpu-nr %d\n", *byte));
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break;
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case hw_pal_nr_cpu_register:
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if (hw_tree_find_property (me, "/openprom/options/smp") == NULL)
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{
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*byte = 1;
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HW_TRACE ((me, "read - nr-cpu %d (not defined)\n", *byte));
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}
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else
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{
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*byte = hw_tree_find_integer_property (me, "/openprom/options/smp");
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HW_TRACE ((me, "read - nr-cpu %d\n", *byte));
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}
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break;
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case hw_pal_read_fifo:
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*byte = hw_pal->input.buffer;
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HW_TRACE ((me, "read - input-fifo %d\n", *byte));
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break;
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case hw_pal_read_status:
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scan_hw_pal (me);
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*byte = hw_pal->input.status;
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HW_TRACE ((me, "read - input-status %d\n", *byte));
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break;
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case hw_pal_write_fifo:
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*byte = hw_pal->output.buffer;
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HW_TRACE ((me, "read - output-fifo %d\n", *byte));
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break;
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case hw_pal_write_status:
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*byte = hw_pal->output.status;
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HW_TRACE ((me, "read - output-status %d\n", *byte));
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break;
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case hw_pal_countdown:
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do_counter_read (me, hw_pal, "countdown",
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&hw_pal->countdown, dest, nr_bytes);
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break;
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case hw_pal_countdown_value:
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do_counter_value (me, hw_pal, "countdown-value",
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&hw_pal->countdown, dest, nr_bytes);
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break;
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case hw_pal_timer:
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do_counter_read (me, hw_pal, "timer",
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&hw_pal->timer, dest, nr_bytes);
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break;
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case hw_pal_timer_value:
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do_counter_value (me, hw_pal, "timer-value",
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&hw_pal->timer, dest, nr_bytes);
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break;
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default:
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HW_TRACE ((me, "read - ???\n"));
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break;
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}
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return nr_bytes;
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}
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static unsigned
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hw_pal_io_write_buffer (struct hw *me,
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const void *source,
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int space,
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unsigned_word addr,
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unsigned nr_bytes)
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{
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hw_pal_device *hw_pal = (hw_pal_device*) hw_data (me);
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unsigned_1 *byte = (unsigned_1 *) source;
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switch (addr & hw_pal_address_mask)
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{
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case hw_pal_reset_register:
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hw_halt (me, sim_exited, byte[0]);
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break;
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case hw_pal_int_register:
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hw_port_event (me,
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INT_PORT + byte[0], /*port*/
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(nr_bytes > 1 ? byte[1] : 0)); /* val */
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break;
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case hw_pal_read_fifo:
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hw_pal->input.buffer = byte[0];
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HW_TRACE ((me, "write - input-fifo %d\n", byte[0]));
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break;
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case hw_pal_read_status:
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hw_pal->input.status = byte[0];
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HW_TRACE ((me, "write - input-status %d\n", byte[0]));
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break;
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case hw_pal_write_fifo:
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write_hw_pal (me, byte[0]);
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HW_TRACE ((me, "write - output-fifo %d\n", byte[0]));
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break;
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case hw_pal_write_status:
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hw_pal->output.status = byte[0];
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HW_TRACE ((me, "write - output-status %d\n", byte[0]));
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break;
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case hw_pal_countdown:
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do_counter_write (me, hw_pal, "countdown",
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&hw_pal->countdown, source, nr_bytes);
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break;
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case hw_pal_timer:
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do_counter_write (me, hw_pal, "timer",
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&hw_pal->timer, source, nr_bytes);
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break;
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}
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return nr_bytes;
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}
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/* instances of the hw_pal struct hw */
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#if NOT_YET
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static void
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hw_pal_instance_delete_callback (hw_instance *instance)
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{
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/* nothing to delete, the hw_pal is attached to the struct hw */
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return;
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}
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#endif
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#if NOT_YET
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static int
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hw_pal_instance_read_callback (hw_instance *instance,
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void *buf,
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unsigned_word len)
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{
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DITRACE (pal, ("read - %s (%ld)", (const char*) buf, (long int) len));
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return sim_io_read_stdin (buf, len);
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}
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#endif
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#if NOT_YET
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static int
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hw_pal_instance_write_callback (hw_instance *instance,
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const void *buf,
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unsigned_word len)
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{
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int i;
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const char *chp = buf;
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hw_pal_device *hw_pal = hw_instance_data (instance);
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DITRACE (pal, ("write - %s (%ld)", (const char*) buf, (long int) len));
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for (i = 0; i < len; i++)
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write_hw_pal (hw_pal, chp[i]);
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sim_io_flush_stdoutput ();
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return i;
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}
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#endif
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#if NOT_YET
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static const hw_instance_callbacks hw_pal_instance_callbacks = {
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hw_pal_instance_delete_callback,
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hw_pal_instance_read_callback,
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hw_pal_instance_write_callback,
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};
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#endif
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#if 0
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static hw_instance *
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hw_pal_create_instance (struct hw *me,
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const char *path,
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const char *args)
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{
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return hw_create_instance_from (me, NULL,
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hw_data (me),
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path, args,
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&hw_pal_instance_callbacks);
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}
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#endif
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static void
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hw_pal_attach_address (struct hw *me,
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int level,
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int space,
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address_word addr,
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address_word nr_bytes,
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struct hw *client)
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{
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hw_pal_device *pal = (hw_pal_device*) hw_data (me);
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pal->disk = client;
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}
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#if 0
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static hw_callbacks const hw_pal_callbacks = {
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{ generic_hw_init_address, },
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{ hw_pal_attach_address, }, /* address */
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|
{ hw_pal_io_read_buffer_callback,
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|
hw_pal_io_write_buffer_callback, },
|
|
{ NULL, }, /* DMA */
|
|
{ NULL, NULL, hw_pal_interrupt_ports }, /* interrupt */
|
|
{ generic_hw_unit_decode,
|
|
generic_hw_unit_encode,
|
|
generic_hw_address_to_attach_address,
|
|
generic_hw_size_to_attach_size },
|
|
hw_pal_create_instance,
|
|
};
|
|
#endif
|
|
|
|
|
|
static void
|
|
hw_pal_finish (struct hw *hw)
|
|
{
|
|
/* create the descriptor */
|
|
hw_pal_device *hw_pal = HW_ZALLOC (hw, hw_pal_device);
|
|
hw_pal->output.status = 1;
|
|
hw_pal->output.buffer = '\0';
|
|
hw_pal->input.status = 0;
|
|
hw_pal->input.buffer = '\0';
|
|
set_hw_data (hw, hw_pal);
|
|
set_hw_attach_address (hw, hw_pal_attach_address);
|
|
set_hw_io_read_buffer (hw, hw_pal_io_read_buffer);
|
|
set_hw_io_write_buffer (hw, hw_pal_io_write_buffer);
|
|
set_hw_ports (hw, hw_pal_ports);
|
|
/* attach ourselves */
|
|
do_hw_attach_regs (hw);
|
|
/* If so configured, enable polled input */
|
|
if (hw_find_property (hw, "poll?") != NULL
|
|
&& hw_find_boolean_property (hw, "poll?"))
|
|
{
|
|
hw_pal->reader = sim_io_poll_read;
|
|
}
|
|
else
|
|
{
|
|
hw_pal->reader = sim_io_read;
|
|
}
|
|
/* tag the periodic timer */
|
|
hw_pal->timer.periodic_p = 1;
|
|
}
|
|
|
|
|
|
const struct hw_descriptor dv_pal_descriptor[] = {
|
|
{ "pal", hw_pal_finish, },
|
|
{ NULL, NULL },
|
|
};
|