8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
214 lines
6.9 KiB
C
214 lines
6.9 KiB
C
/* Simulator header for cgen parallel support.
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Copyright (C) 1999-2013 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This file is part of the GNU instruction set simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CGEN_PAR_H
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#define CGEN_PAR_H
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/* Kinds of writes stored on the write queue. */
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enum cgen_write_queue_kind {
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CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
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CGEN_PC_WRITE,
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CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE,
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CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
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CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE,
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CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
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CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE,
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CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE,
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CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE,
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CGEN_NUM_WRITE_KINDS
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};
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/* Element of the write queue. */
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typedef struct {
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enum cgen_write_queue_kind kind; /* Used to select union member below. */
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IADDR insn_address; /* Address of the insn performing the write. */
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unsigned32 flags; /* Target specific flags. */
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long word1; /* Target specific field. */
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union {
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struct {
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BI *target;
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BI value;
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} bi_write;
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struct {
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UQI *target;
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QI value;
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} qi_write;
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struct {
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SI *target;
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SI value;
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} si_write;
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struct {
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SI *target;
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SF value;
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} sf_write;
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struct {
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USI value;
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} pc_write;
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struct {
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UINT regno;
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UHI value;
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void (*function)(SIM_CPU *, UINT, UHI);
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} fn_hi_write;
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struct {
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UINT regno;
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SI value;
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void (*function)(SIM_CPU *, UINT, USI);
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} fn_si_write;
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struct {
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UINT regno;
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SF value;
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void (*function)(SIM_CPU *, UINT, SF);
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} fn_sf_write;
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struct {
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UINT regno;
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DI value;
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void (*function)(SIM_CPU *, UINT, DI);
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} fn_di_write;
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struct {
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UINT regno;
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DF value;
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void (*function)(SIM_CPU *, UINT, DF);
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} fn_df_write;
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struct {
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UINT regno;
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SI value[4];
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void (*function)(SIM_CPU *, UINT, SI *);
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} fn_xi_write;
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struct {
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USI value;
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void (*function)(SIM_CPU *, USI);
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} fn_pc_write;
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struct {
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SI address;
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QI value;
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} mem_qi_write;
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struct {
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SI address;
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HI value;
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} mem_hi_write;
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struct {
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SI address;
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SI value;
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} mem_si_write;
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struct {
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SI address;
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DI value;
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} mem_di_write;
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struct {
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SI address;
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DF value;
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} mem_df_write;
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struct {
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SI address;
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SI value[4];
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} mem_xi_write;
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struct {
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SI address;
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QI value;
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void (*function)(SIM_CPU *, IADDR, SI, QI);
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} fn_mem_qi_write;
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struct {
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SI address;
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HI value;
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void (*function)(SIM_CPU *, IADDR, SI, HI);
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} fn_mem_hi_write;
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struct {
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SI address;
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SI value;
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void (*function)(SIM_CPU *, IADDR, SI, SI);
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} fn_mem_si_write;
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struct {
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SI address;
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DI value;
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void (*function)(SIM_CPU *, IADDR, SI, DI);
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} fn_mem_di_write;
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struct {
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SI address;
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DF value;
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void (*function)(SIM_CPU *, IADDR, SI, DF);
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} fn_mem_df_write;
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struct {
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SI address;
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SI value[4];
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void (*function)(SIM_CPU *, IADDR, SI, SI *);
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} fn_mem_xi_write;
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} kinds;
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} CGEN_WRITE_QUEUE_ELEMENT;
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#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
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#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
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#define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags)
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#define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1)
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extern void cgen_write_queue_element_execute (
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SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
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);
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/* Instance of the queue for parallel write-after support. */
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/* FIXME: Should be dynamic? */
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#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */
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typedef struct {
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int index;
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CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
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} CGEN_WRITE_QUEUE;
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#define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
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#define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
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#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
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#define CGEN_WRITE_QUEUE_NEXT(queue) ( \
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(queue)->index < CGEN_WRITE_QUEUE_SIZE \
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? &(queue)->q[(queue)->index++] \
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: cgen_write_queue_overflow (queue) \
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)
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extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
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/* Functions for queuing writes. Used by semantic code. */
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extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
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extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
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extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
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extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
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extern void sim_queue_pc_write (SIM_CPU *, USI);
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extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
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extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI);
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extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF);
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extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
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extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF);
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extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
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extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);
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extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
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extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
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extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
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extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
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extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
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extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *);
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extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI);
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extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI);
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extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI);
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extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI);
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extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF);
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extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *);
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#endif /* CGEN_PAR_H */
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