391 lines
14 KiB
C
391 lines
14 KiB
C
/* MIPS Simulator definition.
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Copyright (C) 1997 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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/* This simulator doesn't cache the Current Instruction Address */
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#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
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#define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA)
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#define SIM_HAVE_BIENDIAN
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#define SIM_HAVE_FLATMEM
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/* hobble some common features for moment */
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#define WITH_PROFILE 0
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#define WITH_TRACE 0
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#define WITH_WATCHPOINTS 1
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#include "sim-basics.h"
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/* dummy - not used */
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typedef int sim_cia;
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#define NULL_CIA 0
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#include "sim-base.h"
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/* Depreciated macros and types for manipulating 64bit values. Use
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../common/sim-bits.h and ../common/sim-endian.h macros instead. */
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typedef signed64 word64;
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typedef unsigned64 uword64;
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#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
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#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
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#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
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#define SET64HI(t) (((uword64)(t))<<32)
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#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
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#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
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/* Sign-extend the given value (e) as a value (b) bits long. We cannot
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assume the HI32bits of the operand are zero, so we must perform a
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mask to ensure we can use the simple subtraction to sign-extend. */
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#define SIGNEXTEND(e,b) \
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(((e) & ((uword64) 1 << ((b) - 1))) \
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? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
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: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1)))
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/* Check if a value will fit within a halfword: */
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#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
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/* windows always looses */
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#include <signal.h>
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#ifndef SIGBUS
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#define SIGBUS SIGSEGV
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#endif
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#ifdef _WIN32
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#define SIGTRAP 5
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#define SIGQUIT 3
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#endif
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/* Floating-point operations: */
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/* FPU registers must be one of the following types. All other values
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are reserved (and undefined). */
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typedef enum {
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fmt_single = 0,
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fmt_double = 1,
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fmt_word = 4,
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fmt_long = 5,
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/* The following are well outside the normal acceptable format
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range, and are used in the register status vector. */
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fmt_unknown = 0x10000000,
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fmt_uninterpreted = 0x20000000,
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} FP_formats;
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unsigned64 value_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats));
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#define ValueFPR(FPR,FMT) value_fpr (sd, (FPR), (FMT))
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void store_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats fmt, unsigned64 value));
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#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, (FPR), (FMT), (VALUE))
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int NaN PARAMS ((unsigned64 op, FP_formats fmt));
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int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
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int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 convert PARAMS ((SIM_DESC sd, int rm, unsigned64 op, FP_formats from, FP_formats to));
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#define Convert(rm,op,from,to) convert(sd,rm,op,from,to)
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struct _sim_cpu {
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/* The following are internal simulator state variables: */
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address_word ipc; /* internal Instruction PC */
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address_word dspc; /* delay-slot PC */
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#define IPC ((STATE_CPU (sd,0))->ipc)
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#define DSPC ((STATE_CPU (sd,0))->dspc)
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/* State of the simulator */
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unsigned int state;
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unsigned int dsstate;
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#define STATE ((STATE_CPU (sd,0))->state)
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#define DSSTATE ((STATE_CPU (sd,0))->dsstate)
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/* This is nasty, since we have to rely on matching the register
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numbers used by GDB. Unfortunately, depending on the MIPS target
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GDB uses different register numbers. We cannot just include the
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relevant "gdb/tm.h" link, since GDB may not be configured before
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the sim world, and also the GDB header file requires too much other
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state. */
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#ifndef TM_MIPS_H
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#define LAST_EMBED_REGNUM (89)
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#define NUM_REGS (LAST_EMBED_REGNUM + 1)
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/* start-sanitize-r5900 */
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#undef NUM_REGS
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#define NUM_REGS (128)
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/* end-sanitize-r5900 */
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#endif
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/* To keep this default simulator simple, and fast, we use a direct
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vector of registers. The internal simulator engine then uses
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manifests to access the correct slot. */
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signed_word registers[LAST_EMBED_REGNUM + 1];
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int register_widths[NUM_REGS];
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#define REGISTERS ((STATE_CPU (sd,0))->registers)
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#define GPR (®ISTERS[0])
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#define FGRIDX (38)
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#define FGR (®ISTERS[FGRIDX])
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#define LO (REGISTERS[33])
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#define HI (REGISTERS[34])
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#define PC (REGISTERS[37])
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#define CAUSE (REGISTERS[36])
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#define SRIDX (32)
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#define SR (REGISTERS[SRIDX]) /* CPU status register */
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#define FCR0IDX (71)
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#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
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#define FCR31IDX (70)
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#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
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#define FCSR (FCR31)
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#define Debug (REGISTERS[86])
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#define DEPC (REGISTERS[87])
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#define EPC (REGISTERS[88])
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#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
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/* The following are pseudonyms for standard registers */
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#define ZERO (REGISTERS[0])
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#define V0 (REGISTERS[2])
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#define A0 (REGISTERS[4])
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#define A1 (REGISTERS[5])
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#define A2 (REGISTERS[6])
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#define A3 (REGISTERS[7])
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#define SP (REGISTERS[29])
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#define RA (REGISTERS[31])
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/* Keep the current format state for each register: */
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FP_formats fpr_state[32];
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#define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
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/* Slots for delayed register updates. For the moment we just have a
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fixed number of slots (rather than a more generic, dynamic
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system). This keeps the simulator fast. However, we only allow
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for the register update to be delayed for a single instruction
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cycle. */
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#define PSLOTS (5) /* Maximum number of instruction cycles */
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int pending_in;
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int pending_out;
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int pending_total;
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int pending_slot_count[PSLOTS];
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int pending_slot_reg[PSLOTS];
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unsigned_word pending_slot_value[PSLOTS];
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#define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
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#define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
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#define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
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#define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
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#define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
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#define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
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/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
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read-write instructions. It is set when a linked load occurs. It
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is tested and cleared by the conditional store. It is cleared
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(during other CPU operations) when a store to the location would
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no longer be atomic. In particular, it is cleared by exception
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return instructions. */
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int llbit;
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#define LLBIT ((STATE_CPU (sd, 0))->llbit)
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/* The HIACCESS and LOACCESS counts are used to ensure that
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corruptions caused by using the HI or LO register to close to a
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following operation are spotted. */
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int hiaccess;
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int loaccess;
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#define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
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#define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
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/* start-sanitize-r5900 */
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int hi1access;
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int lo1access;
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#define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
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#define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
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/* end-sanitize-r5900 */
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#if 1
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/* The 4300 and a few other processors have interlocks on hi/lo
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register reads, and hence do not have this problem. To avoid
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spurious warnings, we just disable this always. */
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#define CHECKHILO(s)
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#else
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unsigned_word HLPC;
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/* If either of the preceding two instructions have accessed the HI
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or LO registers, then the values they see should be
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undefined. However, to keep the simulator world simple, we just
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let them use the value read and raise a warning to notify the
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user: */
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#define CHECKHILO(s) {\
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if ((HIACCESS != 0) || (LOACCESS != 0)) \
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sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
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}
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/* end-sanitize-r5900 */
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#undef CHECKHILO
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#define CHECKHILO(s) {\
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if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
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sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
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}
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/* end-sanitize-r5900 */
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#endif
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/* start-sanitize-r5900 */
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/* The R5900 has 128 bit registers, but the hi 64 bits are only
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touched by multimedia (MMI) instructions. The normal mips
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instructions just use the lower 64 bits. To avoid changing the
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older parts of the simulator to handle this weirdness, the high
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64 bits of each register are kept in a separate array
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(registers1). The high 64 bits of any register are by convention
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refered by adding a '1' to the end of the normal register's name.
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So LO still refers to the low 64 bits of the LO register, LO1
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refers to the high 64 bits of that same register. */
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signed_word registers1[LAST_EMBED_REGNUM + 1];
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#define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
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#define GPR1 (®ISTERS1[0])
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#define LO1 (REGISTERS1[32])
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#define HI1 (REGISTERS1[33])
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#define REGISTER_SA (124)
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unsigned_word sa; /* the shift amount register */
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#define SA ((STATE_CPU (sd, 0))->sa)
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/* end-sanitize-r5900 */
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sim_cpu_base base;
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};
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/* MIPS specific simulator watch config */
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void watch_options_install PARAMS ((SIM_DESC sd));
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struct swatch {
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sim_event *pc;
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sim_event *clock;
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sim_event *cycles;
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};
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/* FIXME: At present much of the simulator is still static */
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struct sim_state {
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struct swatch watch;
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sim_cpu cpu[1];
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#if (WITH_SMP)
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#define STATE_CPU(sd,n) (&(sd)->cpu[n])
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#else
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#define STATE_CPU(sd,n) (&(sd)->cpu[0])
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#endif
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sim_state_base base;
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};
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/* Exceptions: */
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/* NOTE: These numbers depend on the processor architecture being
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simulated: */
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#define Interrupt (0)
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#define TLBModification (1)
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#define TLBLoad (2)
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#define TLBStore (3)
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#define AddressLoad (4)
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#define AddressStore (5)
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#define InstructionFetch (6)
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#define DataReference (7)
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#define SystemCall (8)
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#define BreakPoint (9)
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#define ReservedInstruction (10)
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#define CoProcessorUnusable (11)
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#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
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#define Trap (13)
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#define FPE (15)
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#define DebugBreakPoint (16)
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#define Watch (23)
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/* The following exception code is actually private to the simulator
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world. It is *NOT* a processor feature, and is used to signal
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run-time errors in the simulator. */
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#define SimulatorFault (0xFFFFFFFF)
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void signal_exception (SIM_DESC sd, int exception, ...);
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#define SignalException(exc,instruction) signal_exception (sd, (exc), (instruction))
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#define SignalExceptionInterrupt() signal_exception (sd, Interrupt)
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#define SignalExceptionInstructionFetch() signal_exception (sd, InstructionFetch)
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#define SignalExceptionAddressStore() signal_exception (sd, AddressStore)
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#define SignalExceptionAddressLoad() signal_exception (sd, AddressLoad)
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#define SignalExceptionSimulatorFault(buf) signal_exception (sd, SimulatorFault, buf)
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#define SignalExceptionFPE() signal_exception (sd, FPE)
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#define SignalExceptionIntegerOverflow() signal_exception (sd, IntegerOverflow)
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#define SignalExceptionCoProcessorUnusable() signal_exception (sd, CoProcessorUnusable)
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/* Co-processor accesses */
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void cop_lw PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, unsigned int memword));
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void cop_ld PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, uword64 memword));
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unsigned int cop_sw PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
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uword64 cop_sd PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
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#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,coproc_num,coproc_reg,memword)
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#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,coproc_num,coproc_reg,memword)
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#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg)
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#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg)
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/* Memory accesses */
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int address_translation PARAMS ((SIM_DESC sd, uword64 vAddr, int IorD, int LorS, uword64 *pAddr, int *CCA, int host, int raw));
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#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
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address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw)
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void load_memory PARAMS ((SIM_DESC sd, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, uword64 pAddr, uword64 vAddr, int IorD, int raw));
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#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
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load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
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void store_memory PARAMS ((SIM_DESC sd, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, uword64 pAddr, uword64 vAddr, int raw));
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#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
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store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
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void cache_op PARAMS ((SIM_DESC sd, int op, uword64 pAddr, uword64 vAddr, unsigned int instruction));
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#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
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#endif
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