607 lines
18 KiB
C
607 lines
18 KiB
C
/* frv simulator fr450 dependent profiling code.
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Copyright (C) 2001, 2004 Free Software Foundation, Inc.
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Contributed by Red Hat
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#define WANT_CPU
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "bfd.h"
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#if WITH_PROFILE_MODEL_P
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#include "profile.h"
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#include "profile-fr400.h"
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int
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frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced)
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{
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return idesc->timing->units[unit_num].done;
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}
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int
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frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk,
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INT out_ICCi_1)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk, out_ICCi_1);
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}
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int
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frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr500. */
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return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk, out_ICCi_1);
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}
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/* icc0-icc4 are the upper 4 fields of the CCR. */
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if (out_ICCi_1 >= 0)
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out_ICCi_1 += 4;
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/* GRk and IACCi_1 have a latency of 1 cycle. */
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cycles = idesc->timing->units[unit_num].done;
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update_GRdouble_latency (cpu, out_GRk, cycles + 1);
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update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
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return cycles;
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}
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int
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frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr500. */
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return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk, out_ICCi_1);
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}
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/* icc0-icc4 are the upper 4 fields of the CCR. */
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if (out_ICCi_1 >= 0)
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out_ICCi_1 += 4;
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/* GRk, ICCi_1 and the divider have a latency of 18 cycles */
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cycles = idesc->timing->units[unit_num].done;
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update_GR_latency (cpu, out_GRk, cycles + 18);
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update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
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update_idiv_resource_latency (cpu, 0, cycles + 18);
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return cycles;
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}
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int
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frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_ICCi_2, INT in_ICCi_3)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
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}
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int
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frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_ICCi_2, INT in_FCCi_2)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
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}
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int
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frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ICCi_3, INT in_FCCi_3)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
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in_ICCi_3, in_FCCi_3);
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}
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int
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frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT out_GRkhi, INT out_GRklo)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
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out_GRkhi, out_GRklo);
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}
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int
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frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT out_GRk, INT out_GRdoublek)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr500. */
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return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk,
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out_GRdoublek);
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}
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cycles = idesc->timing->units[unit_num].done;
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/* The latency of GRk for a load will depend on how long it takes to retrieve
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the the data from the cache or memory. */
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update_GR_latency_for_load (cpu, out_GRk, cycles);
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update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
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if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
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{
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/* GNER has a latency of 2 cycles. */
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update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
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update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
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}
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return cycles;
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}
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int
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frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_GRk, INT in_GRdoublek)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_GRk, in_GRdoublek);
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}
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int
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frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT out_FRk, INT out_FRdoublek)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_FRk, out_FRdoublek);
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}
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int
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frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_FRk, INT in_FRdoublek)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_FRk, in_FRdoublek);
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}
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int
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frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk);
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}
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int
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frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRk, INT out_GRj)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr400. */
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return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced,
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in_FRk, out_GRj);
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}
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/* The latency of GRj is 1 cycle. */
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cycles = idesc->timing->units[unit_num].done;
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update_GR_latency (cpu, out_GRj, cycles + 1);
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return cycles;
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}
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int
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frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_spr, INT out_GRj)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
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in_spr, out_GRj);
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}
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int
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frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRj, INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced,
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in_GRj, out_FRk);
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}
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int
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frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRj, INT out_spr)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
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in_GRj, out_spr);
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}
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int
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frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT in_FRj,
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INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_FRk);
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}
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int
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frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT in_FRj,
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INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_FRk);
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}
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int
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frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT out_FRkhi, INT out_FRklo)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced,
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out_FRkhi, out_FRklo);
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}
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int
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frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT in_FRj,
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INT out_ACC40Sk, INT out_ACC40Uk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_ACC40Sk,
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out_ACC40Uk);
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}
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int
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frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT in_FRj,
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INT out_ACC40Sk, INT out_ACC40Uk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_ACC40Sk,
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out_ACC40Uk);
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}
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int
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frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACC40Si, INT out_ACC40Sk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced,
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in_ACC40Si, out_ACC40Sk);
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}
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int
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frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACC40Si, INT out_ACC40Sk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num,
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referenced, in_ACC40Si,
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out_ACC40Sk);
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}
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int
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frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACC40Si, INT out_ACC40Sk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num,
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referenced, in_ACC40Si,
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out_ACC40Sk);
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}
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int
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frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACC40Si, INT out_ACC40Sk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num,
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referenced, in_ACC40Si,
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out_ACC40Sk);
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}
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int
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frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT in_FRj,
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INT out_FRk)
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{
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/* Modelling is the same as media unit 1. */
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return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_FRk);
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}
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int
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frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced,
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in_FRi, out_FRk);
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}
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int
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frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRi, INT in_FRj,
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INT out_FRk)
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{
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/* Modelling is the same as media unit 1. */
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return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_FRk);
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}
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int
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frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACC40Si, INT in_FRj,
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INT out_ACC40Sk, INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
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in_ACC40Si, in_FRj,
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out_ACC40Sk, out_FRk);
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}
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int
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frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACCGi, INT in_FRinti,
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INT out_ACCGk, INT out_FRintk)
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{
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/* Modelling is the same as media-4 unit except use accumulator guards
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as input instead of accumulators. */
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return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced,
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in_ACCGi, in_FRinti,
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out_ACCGk, out_FRintk);
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}
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int
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frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ACC40Si, INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num,
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referenced, in_ACC40Si,
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out_FRk);
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}
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int
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frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced)
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{
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int cycles;
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int acc;
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FRV_PROFILE_STATE *ps;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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return 0;
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/* The preprocessing can execute right away. */
|
|
cycles = idesc->timing->units[unit_num].done;
|
|
|
|
ps = CPU_PROFILE_STATE (cpu);
|
|
|
|
/* The post processing must wait for any pending ACC writes. */
|
|
ps->post_wait = cycles;
|
|
for (acc = 0; acc < 4; acc++)
|
|
post_wait_for_ACC (cpu, acc);
|
|
for (acc = 8; acc < 12; acc++)
|
|
post_wait_for_ACC (cpu, acc);
|
|
|
|
for (acc = 0; acc < 4; acc++)
|
|
{
|
|
update_ACC_latency (cpu, acc, ps->post_wait);
|
|
update_ACC_ptime (cpu, acc, 2);
|
|
}
|
|
for (acc = 8; acc < 12; acc++)
|
|
{
|
|
update_ACC_latency (cpu, acc, ps->post_wait);
|
|
update_ACC_ptime (cpu, acc, 2);
|
|
}
|
|
|
|
return cycles;
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_FRi, INT out_FRk)
|
|
{
|
|
/* Modelling for this unit is the same as for fr400. */
|
|
return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced,
|
|
in_FRi, out_FRk);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_FRinti, INT in_FRintj,
|
|
INT out_FCCk)
|
|
{
|
|
/* Modelling for this unit is the same as for fr400. */
|
|
return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced,
|
|
in_FRinti, in_FRintj, out_FCCk);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_FRi,
|
|
INT out_FRk)
|
|
{
|
|
/* Modelling for this unit is the same as for fr400. */
|
|
return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num,
|
|
referenced, in_FRi, out_FRk);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_FRj,
|
|
INT out_FRk)
|
|
{
|
|
/* Modelling for this unit is the same as for fr400. */
|
|
return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num,
|
|
referenced, in_FRj, out_FRk);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced,
|
|
INT in_GRi, INT in_GRj)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
|
|
in_GRi, in_GRj);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
|
|
}
|
|
|
|
int
|
|
frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,
|
|
int unit_num, int referenced)
|
|
{
|
|
/* Modelling for this unit is the same as for fr500. */
|
|
return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
|
|
}
|
|
|
|
#endif /* WITH_PROFILE_MODEL_P */
|