26d97720ed
* config/tc-arm.c (parse_address_main): Handle -0 offsets. (encode_arm_addr_mode_2): Set default sign of zero here ... (encode_arm_addr_mode_3): ... and here. (encode_arm_cp_address): ... and here. (md_apply_fix): Use default sign of zero here. gas/testsuite/ * gas/arm/inst.d: Adjust for signed zero offsets. * gas/arm/ldst-offset0.d: New test. * gas/arm/ldst-offset0.s: New test. * gas/arm/offset-1.d: New test. * gas/arm/offset-1.s: New test. ld/testsuite/ Adjust tests for zero offset formatting. * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust. * ld-arm/farcall-arm-arm-pic-veneer.d: Adjust. * ld-arm/farcall-arm-thumb.d: Adjust. * ld-arm/farcall-group-size2.d: Adjust. * ld-arm/farcall-group.d: Adjust. * ld-arm/farcall-mix.d: Adjust. * ld-arm/farcall-mix2.d: Adjust. * ld-arm/farcall-mixed-lib-v4t.d: Adjust. * ld-arm/farcall-mixed-lib.d: Adjust. * ld-arm/farcall-thumb-arm-blx-pic-veneer.d: Adjust. * ld-arm/farcall-thumb-arm-pic-veneer.d: Adjust. * ld-arm/farcall-thumb-thumb.d: Adjust. * ld-arm/ifunc-10.dd: Adjust. * ld-arm/ifunc-3.dd: Adjust. * ld-arm/ifunc-4.dd: Adjust. * ld-arm/ifunc-5.dd: Adjust. * ld-arm/ifunc-6.dd: Adjust. * ld-arm/ifunc-7.dd: Adjust. * ld-arm/ifunc-8.dd: Adjust. * ld-arm/jump-reloc-veneers-long.d: Adjust. * ld-arm/tls-longplt-lib.d: Adjust. * ld-arm/tls-thumb1.d: Adjust. opcodes/ * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 as address offset. (print_arm_address): Likewise. Elide positive #0 appropriately. (print_insn_arm): Likewise.
32 lines
942 B
Makefile
32 lines
942 B
Makefile
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.*
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Disassembly of section \.plt:
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00008000 <\.plt>:
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8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
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8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <foo-0xfe0>
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8008: e08fe00e add lr, pc, lr
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800c: e5bef008 ldr pc, \[lr, #8\]!
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8010: 00001004 \.word 0x00001004
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8014: 4778 bx pc
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8016: 46c0 nop ; \(mov r8, r8\)
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8018: e28fc600 add ip, pc, #0
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801c: e28cca01 add ip, ip, #4096 ; 0x1000
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8020: e5bcf000 ldr pc, \[ip, #0\]!
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Disassembly of section \.text:
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00008ff0 <foo>:
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8ff0: 46c0 nop ; \(mov r8, r8\)
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8ff2: f240 0000 movw r0, #0
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8ff6: f240 0000 movw r0, #0
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8ffa: f240 0000 movw r0, #0
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8ffe: f000 b803 b\.w 9008 <foo\+0x18>
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9002: 0000 movs r0, r0
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9004: 0000 movs r0, r0
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9006: 0000 movs r0, r0
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9008: d001 beq\.n 900e <foo\+0x1e>
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900a: f7ff bffa b\.w 9002 <foo\+0x12>
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900e: f7ff b801 b\.w 8014 <foo-0xfdc>
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