6fd4f6ccfe
* config/tc-h8300.h (H_TICK_HEX): Define. * config/tc-h8300.c (OPTION_H_TICK_HEX): New. (md_longopts): Add "-h-tick-hex". (md_parse_option): Support it. * doc/c-h8300.texi (H8/300 Options): Document it. * doc/as.texinfo (Overview): Likewise. * config/tc-sh.h (H_TICK_HEX): Define. * config/tc-sh.c (OPTION_H_TICK_HEX): New. (md_longopts): Add "-h-tick-hex". (md_parse_option): Support it. * doc/c-sh.texi (SH Options): Document it. * doc/c-sh64.texi (SH64 Options): Document it. * doc/as.texinfo (Overview): Likewise.
123 lines
3.1 KiB
Text
123 lines
3.1 KiB
Text
@c Copyright 2005
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node M32C-Dependent
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@chapter M32C Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter M32C Dependent Features
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@end ifclear
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@cindex M32C support
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@code{@value{AS}} can assemble code for several different members of
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the Renesas M32C family. Normally the default is to assemble code for
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the M16C microprocessor. The @code{-m32c} option may be used to
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change the default to the M32C microprocessor.
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@menu
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* M32C-Opts:: M32C Options
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* M32C-Modifiers:: Symbolic Operand Modifiers
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@end menu
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@node M32C-Opts
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@section M32C Options
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@cindex options, M32C
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@cindex M32C options
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The Renesas M32C version of @code{@value{AS}} has these
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machine-dependent options:
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@table @code
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@item -m32c
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@cindex @samp{-m32c} option, M32C
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@cindex architecture options, M32C
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@cindex M32C architecture option
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Assemble M32C instructions.
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@item -m16c
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@cindex @samp{-m16c} option, M16C
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@cindex architecture options, M16C
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@cindex M16C architecture option
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Assemble M16C instructions (default).
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@item -relax
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Enable support for link-time relaxations.
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@item -h-tick-hex
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Support H'00 style hex constants in addition to 0x00 style.
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@end table
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@node M32C-Modifiers
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@section Symbolic Operand Modifiers
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@cindex M32C modifiers
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@cindex syntax, M32C
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The assembler supports several modifiers when using symbol addresses
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in M32C instruction operands. The general syntax is the following:
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@smallexample
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%modifier(symbol)
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@end smallexample
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@table @code
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@cindex symbol modifiers
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@item %dsp8
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@itemx %dsp16
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These modifiers override the assembler's assumptions about how big a
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symbol's address is. Normally, when it sees an operand like
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@samp{sym[a0]} it assumes @samp{sym} may require the widest
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displacement field (16 bits for @samp{-m16c}, 24 bits for
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@samp{-m32c}). These modifiers tell it to assume the address will fit
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in an 8 or 16 bit (respectively) unsigned displacement. Note that, of
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course, if it doesn't actually fit you will get linker errors. Example:
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@smallexample
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mov.w %dsp8(sym)[a0],r1
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mov.b #0,%dsp8(sym)[a0]
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@end smallexample
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@item %hi8
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This modifier allows you to load bits 16 through 23 of a 24 bit
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address into an 8 bit register. This is useful with, for example, the
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M16C @samp{smovf} instruction, which expects a 20 bit address in
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@samp{r1h} and @samp{a0}. Example:
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@smallexample
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mov.b #%hi8(sym),r1h
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mov.w #%lo16(sym),a0
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smovf.b
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@end smallexample
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@item %lo16
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Likewise, this modifier allows you to load bits 0 through 15 of a 24
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bit address into a 16 bit register.
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@item %hi16
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This modifier allows you to load bits 16 through 31 of a 32 bit
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address into a 16 bit register. While the M32C family only has 24
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bits of address space, it does support addresses in pairs of 16 bit
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registers (like @samp{a1a0} for the @samp{lde} instruction). This
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modifier is for loading the upper half in such cases. Example:
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@smallexample
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mov.w #%hi16(sym),a1
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mov.w #%lo16(sym),a0
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@dots{}
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lde.w [a1a0],r1
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@end smallexample
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@end table
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