d2a7c97aaf
* i386-tdep.c: Include "elf-bfd.h". (process_note_abi_tag_sections): New function. (i386_gdbarch_init): Add code to recognize various OS/ABI combinations.
116 lines
3.6 KiB
C
116 lines
3.6 KiB
C
/* Target-dependent code for GDB, the GNU debugger.
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Copyright 2001
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#ifndef I386_TDEP_H
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#define I386_TDEP_H
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/* GDB's i386 target supports both the 32-bit Intel Architecture
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(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
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a similar register layout for both.
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- General purpose registers
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- FPU data registers
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- FPU control registers
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- SSE data registers
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- SSE control register
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The general purpose registers for the x86-64 architecture are quite
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different from IA-32. Therefore, the FP0_REGNUM target macro
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determines the register number at which the FPU data registers
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start. The number of FPU data and control registers is the same
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for both architectures. The number of SSE registers however,
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differs and is determined by the num_xmm_regs member of `struct
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gdbarch_tdep'. */
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/* i386 architecture specific information. */
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struct gdbarch_tdep
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{
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/* OS/ABI. */
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int os_ident;
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/* Number of SSE registers. */
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int num_xmm_regs;
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};
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/* Floating-point registers. */
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#define FPU_REG_RAW_SIZE 10
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/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
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(at most) in the FPU, but are zero-extended to 32 bits in GDB's
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register cache. */
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/* "Generic" floating point control register. */
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#define FPC_REGNUM (FP0_REGNUM + 8)
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/* FPU control word. */
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#define FCTRL_REGNUM FPC_REGNUM
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/* FPU status word. */
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#define FSTAT_REGNUM (FPC_REGNUM + 1)
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/* FPU register tag word. */
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#define FTAG_REGNUM (FPC_REGNUM + 2)
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/* FPU instruction's code segment selector, called "FPU Instruction
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Pointer Selector" in the IA-32 manuals. */
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#define FISEG_REGNUM (FPC_REGNUM + 3)
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/* FPU instruction's offset within segment. */
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#define FIOFF_REGNUM (FPC_REGNUM + 4)
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/* FPU operand's data segment. */
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#define FOSEG_REGNUM (FPC_REGNUM + 5)
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/* FPU operand's offset within segment */
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#define FOOFF_REGNUM (FPC_REGNUM + 6)
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/* FPU opcode, bottom eleven bits. */
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#define FOP_REGNUM (FPC_REGNUM + 7)
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/* Return non-zero if N corresponds to a FPU data registers. */
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#define FP_REGNUM_P(n) (FP0_REGNUM <= (n) && (n) < FPC_REGNUM)
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/* Return non-zero if N corresponds to a FPU control register. */
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#define FPC_REGNUM_P(n) (FPC_REGNUM <= (n) && (n) < XMM0_REGNUM)
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/* SSE registers. */
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/* First SSE data register. */
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#define XMM0_REGNUM (FPC_REGNUM + 8)
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/* SSE control/status register. */
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#define MXCSR_REGNUM \
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(XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs)
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/* Return non-zero if N corresponds to a SSE data register. */
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#define SSE_REGNUM_P(n) (XMM0_REGNUM <= (n) && (n) < MXCSR_REGNUM)
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/* FIXME: kettenis/2001-11-24: Obsolete macro's. */
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#define FCS_REGNUM FISEG_REGNUM
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#define FCOFF_REGNUM FIOFF_REGNUM
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#define FDS_REGNUM FOSEG_REGNUM
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#define FDOFF_REGNUM FOOFF_REGNUM
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#define IS_FP_REGNUM(n) FP_REGNUM_P (n)
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#define IS_FPU_CTRL_REGNUM(n) FPC_REGNUM_P (n)
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#define IS_SSE_REGNUM(n) SSE_REGNUM_P (n)
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#endif /* i386-tdep.h */
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