386 lines
11 KiB
C
386 lines
11 KiB
C
/* Definitions to make GDB run on a mips box under Mach 3.0
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Copyright (C) 1992 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Mach specific routines for little endian mips (e.g. pmax)
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* running Mach 3.0
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*
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* Author: Jukka Virtanen <jtv@hut.fi>
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*/
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#include "defs.h"
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#include "inferior.h"
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#include <stdio.h>
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#include <mach.h>
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#include <mach/message.h>
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#include <mach/exception.h>
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#include <mach_error.h>
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/* Find offsets to thread states at compile time.
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* If your compiler does not grok this, check the hand coded
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* offsets and use them.
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*/
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#if 1
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#define REG_OFFSET(reg) (int)(&((struct mips_thread_state *)0)->reg)
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#define CREG_OFFSET(reg) (int)(&((struct mips_float_state *)0)->reg)
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#define EREG_OFFSET(reg) (int)(&((struct mips_exc_state *)0)->reg)
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/* at reg_offset[i] is the offset to the mips_thread_state
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* location where the gdb registers[i] is stored.
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*
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* -1 means mach does not save it anywhere.
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*/
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static int reg_offset[] =
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{
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/* zero at v0 v1 */
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-1, REG_OFFSET(r1), REG_OFFSET(r2), REG_OFFSET(r3),
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/* a0 a1 a2 a3 */
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REG_OFFSET(r4), REG_OFFSET(r5), REG_OFFSET(r6), REG_OFFSET(r7),
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/* t0 t1 t2 t3 */
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REG_OFFSET(r8), REG_OFFSET(r9), REG_OFFSET(r10), REG_OFFSET(r11),
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/* t4 t5 t6 t7 */
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REG_OFFSET(r12), REG_OFFSET(r13), REG_OFFSET(r14), REG_OFFSET(r15),
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/* s0 s1 s2 s3 */
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REG_OFFSET(r16), REG_OFFSET(r17), REG_OFFSET(r18), REG_OFFSET(r19),
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/* s4 s5 s6 s7 */
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REG_OFFSET(r20), REG_OFFSET(r21), REG_OFFSET(r22), REG_OFFSET(r23),
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/* t8 t9 k0 k1 */
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REG_OFFSET(r24), REG_OFFSET(r25), REG_OFFSET(r26), REG_OFFSET(r27),
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/* gp sp s8(30) == fp(72) ra */
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REG_OFFSET(r28), REG_OFFSET(r29), REG_OFFSET(r30), REG_OFFSET(r31),
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/* sr(32) PS_REGNUM */
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EREG_OFFSET(coproc_state),
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/* lo(33) hi(34) */
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REG_OFFSET(mdlo), REG_OFFSET(mdhi),
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/* bad(35) cause(36) pc(37) */
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EREG_OFFSET(address), EREG_OFFSET(cause), REG_OFFSET(pc),
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/* f0(38) f1(39) f2(40) f3(41) */
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CREG_OFFSET(r0), CREG_OFFSET(r1), CREG_OFFSET(r2), CREG_OFFSET(r3),
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CREG_OFFSET(r4), CREG_OFFSET(r5), CREG_OFFSET(r6), CREG_OFFSET(r7),
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CREG_OFFSET(r8), CREG_OFFSET(r9), CREG_OFFSET(r10), CREG_OFFSET(r11),
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CREG_OFFSET(r12), CREG_OFFSET(r13), CREG_OFFSET(r14), CREG_OFFSET(r15),
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CREG_OFFSET(r16), CREG_OFFSET(r17), CREG_OFFSET(r18), CREG_OFFSET(r19),
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CREG_OFFSET(r20), CREG_OFFSET(r21), CREG_OFFSET(r22), CREG_OFFSET(r23),
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CREG_OFFSET(r24), CREG_OFFSET(r25), CREG_OFFSET(r26), CREG_OFFSET(r27),
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CREG_OFFSET(r28), CREG_OFFSET(r29), CREG_OFFSET(r30), CREG_OFFSET(r31),
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/* fsr(70) fir(71) fp(72) == s8(30) */
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CREG_OFFSET(csr), CREG_OFFSET(esr), REG_OFFSET(r30)
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};
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#else
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/* If the compiler does not grok the above defines */
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static int reg_offset[] =
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{
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/* mach_thread_state offsets: */
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-1, 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56,
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60, 64, 68, 72, 76, 80, 84, 88, 92, 96,100,104, 108,112,116,120,
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/*sr, lo, hi,addr,cause,pc */
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8,124,128, 4, 0,132,
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/* mach_float_state offsets: */
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0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
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64, 68, 72, 76, 80, 84, 88, 92, 96,100,104,108, 112,116,120,124,
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/*fsr,fir*/
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128,132,
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/* FP_REGNUM pseudo maps to s8==r30 in mach_thread_state */
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116
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};
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#endif
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/* Fetch COUNT contiguous registers from thread STATE starting from REGNUM
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* Caller knows that the regs handled in one transaction are of same size.
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*/
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#define FETCH_REGS(state, regnum, count) \
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memcpy (®isters[REGISTER_BYTE (regnum)], \
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(char *)state+reg_offset[ regnum ], \
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count*sizeof (REGISTER_TYPE))
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/* Store COUNT contiguous registers to thread STATE starting from REGNUM */
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#define STORE_REGS(state, regnum, count) \
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memcpy ((char *)state+reg_offset[ regnum ], \
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®isters[REGISTER_BYTE (regnum)], \
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count*sizeof (REGISTER_TYPE))
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#define REGS_ALL -1
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#define REGS_NORMAL 1
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#define REGS_EXC 2
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#define REGS_COP1 4
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/* Hardware regs that matches FP_REGNUM */
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#define MACH_FP_REGNUM 30
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/* Fech thread's registers. if regno == -1, fetch all regs */
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void
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fetch_inferior_registers (regno)
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int regno;
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{
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kern_return_t ret;
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thread_state_data_t state;
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struct mips_exc_state exc_state;
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int stateCnt = MIPS_THREAD_STATE_COUNT;
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int which_regs = 0; /* A bit mask */
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if (! MACH_PORT_VALID (current_thread))
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error ("fetch inferior registers: Invalid thread");
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if (regno < -1 || regno >= NUM_REGS)
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error ("invalid register %d supplied to fetch_inferior_registers", regno);
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if (regno == -1)
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which_regs = REGS_ALL;
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else if (regno == ZERO_REGNUM)
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{
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int zero = 0;
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supply_register (ZERO_REGNUM, &zero);
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return;
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}
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else if ((ZERO_REGNUM < regno && regno < PS_REGNUM)
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|| regno == FP_REGNUM
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|| regno == LO_REGNUM
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|| regno == HI_REGNUM
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|| regno == PC_REGNUM)
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which_regs = REGS_NORMAL;
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else if (FP0_REGNUM <= regno && regno <= FCRIR_REGNUM)
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which_regs = REGS_COP1 | REGS_EXC;
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else
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which_regs = REGS_EXC;
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/* fetch regs saved to mips_thread_state */
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if (which_regs & REGS_NORMAL)
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{
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ret = thread_get_state (current_thread,
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MIPS_THREAD_STATE,
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state,
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&stateCnt);
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CHK ("fetch inferior registers: thread_get_state", ret);
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if (which_regs == REGS_NORMAL)
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{
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/* Fetch also FP_REGNUM if fetching MACH_FP_REGNUM and vice versa */
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if (regno == MACH_FP_REGNUM || regno == FP_REGNUM)
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{
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supply_register (FP_REGNUM,
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(char *)state+reg_offset[ MACH_FP_REGNUM ]);
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supply_register (MACH_FP_REGNUM,
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(char *)state+reg_offset[ MACH_FP_REGNUM ]);
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}
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else
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supply_register (regno,
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(char *)state+reg_offset[ regno ]);
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return;
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}
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/* ZERO_REGNUM is always zero */
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*(int *) registers = 0;
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/* Copy thread saved regs 1..31 to gdb's reg value array
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* Luckily, they are contiquous
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*/
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FETCH_REGS (state, 1, 31);
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/* Copy mdlo and mdhi */
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FETCH_REGS (state, LO_REGNUM, 2);
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/* Copy PC */
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FETCH_REGS (state, PC_REGNUM, 1);
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/* Mach 3.0 saves FP to MACH_FP_REGNUM.
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* For some reason gdb wants to assign a pseudo register for it.
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*/
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FETCH_REGS (state, FP_REGNUM, 1);
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}
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/* Read exc state. Also read if need to fetch floats */
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if (which_regs & REGS_EXC)
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{
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stateCnt = MIPS_EXC_STATE_COUNT;
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ret = thread_get_state (current_thread,
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MIPS_EXC_STATE,
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(thread_state_t) &exc_state,
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&stateCnt);
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CHK ("fetch inferior regs (exc): thread_get_state", ret);
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/* We need to fetch exc_state to see if the floating
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* state is valid for the thread.
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*/
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/* cproc_state: Which coprocessors the thread uses */
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supply_register (PS_REGNUM,
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(char *)&exc_state+reg_offset[ PS_REGNUM ]);
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if (which_regs == REGS_EXC || which_regs == REGS_ALL)
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{
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supply_register (BADVADDR_REGNUM,
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(char *)&exc_state+reg_offset[ BADVADDR_REGNUM ]);
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supply_register (CAUSE_REGNUM,
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(char *)&exc_state+reg_offset[ CAUSE_REGNUM ]);
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if (which_regs == REGS_EXC)
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return;
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}
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}
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if (which_regs & REGS_COP1)
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{
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/* If the thread does not have saved COPROC1, set regs to zero */
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if (! (exc_state.coproc_state & MIPS_STATUS_USE_COP1))
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bzero (®isters[ REGISTER_BYTE (FP0_REGNUM) ],
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sizeof (struct mips_float_state));
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else
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{
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stateCnt = MIPS_FLOAT_STATE_COUNT;
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ret = thread_get_state (current_thread,
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MIPS_FLOAT_STATE,
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state,
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&stateCnt);
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CHK ("fetch inferior regs (floats): thread_get_state", ret);
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if (regno != -1)
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{
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supply_register (regno,
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(char *)state+reg_offset[ regno ]);
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return;
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}
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FETCH_REGS (state, FP0_REGNUM, 34);
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}
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}
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/* All registers are valid, if not returned yet */
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registers_fetched ();
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}
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/* Store gdb's view of registers to the thread.
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* All registers are always valid when entering here.
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* @@ ahem, maybe that is too strict, we could validate the necessary ones
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* here.
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*
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* Hmm. It seems that gdb set $reg=value command first reads everything,
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* then sets the reg and then stores everything. -> we must make sure
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* that the immutable registers are not changed by reading them first.
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*/
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void
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store_inferior_registers (regno)
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register int regno;
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{
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thread_state_data_t state;
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kern_return_t ret;
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if (! MACH_PORT_VALID (current_thread))
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error ("store inferior registers: Invalid thread");
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/* Check for read only regs.
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* @@ If some of these is can be changed, fix this
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*/
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if (regno == ZERO_REGNUM ||
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regno == PS_REGNUM ||
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regno == BADVADDR_REGNUM ||
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regno == CAUSE_REGNUM ||
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regno == FCRIR_REGNUM)
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{
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message ("You can not alter read-only register `%s'",
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reg_names[ regno ]);
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fetch_inferior_registers (regno);
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return;
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}
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if (regno == -1)
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{
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/* Don't allow these to change */
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/* ZERO_REGNUM */
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*(int *)registers = 0;
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fetch_inferior_registers (PS_REGNUM);
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fetch_inferior_registers (BADVADDR_REGNUM);
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fetch_inferior_registers (CAUSE_REGNUM);
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fetch_inferior_registers (FCRIR_REGNUM);
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}
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if (regno == -1 || (ZERO_REGNUM < regno && regno <= PC_REGNUM))
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{
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#if 1
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/* Mach 3.0 saves thread's FP to MACH_FP_REGNUM.
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* GDB wants assigns a pseudo register FP_REGNUM for frame pointer.
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*
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* @@@ Here I assume (!) that gdb's FP has the value that
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* should go to threads frame pointer. If not true, this
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* fails badly!!!!!
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*/
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memcpy (®isters[REGISTER_BYTE (MACH_FP_REGNUM)],
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®isters[REGISTER_BYTE (FP_REGNUM)],
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REGISTER_RAW_SIZE (FP_REGNUM));
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#endif
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/* Save gdb's regs 1..31 to thread saved regs 1..31
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* Luckily, they are contiquous
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*/
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STORE_REGS (state, 1, 31);
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/* Save mdlo, mdhi */
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STORE_REGS (state, LO_REGNUM, 2);
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/* Save PC */
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STORE_REGS (state, PC_REGNUM, 1);
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ret = thread_set_state (current_thread,
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MIPS_THREAD_STATE,
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state,
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MIPS_FLOAT_STATE_COUNT);
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CHK ("store inferior regs : thread_set_state", ret);
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}
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if (regno == -1 || regno >= FP0_REGNUM)
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{
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/* If thread has floating state, save it */
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if (read_register (PS_REGNUM) & MIPS_STATUS_USE_COP1)
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{
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/* Do NOT save FCRIR_REGNUM */
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STORE_REGS (state, FP0_REGNUM, 33);
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ret = thread_set_state (current_thread,
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MIPS_FLOAT_STATE,
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state,
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MIPS_FLOAT_STATE_COUNT);
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CHK ("store inferior registers (floats): thread_set_state", ret);
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}
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else if (regno != -1)
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message
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("Thread does not use floating point unit, floating regs not saved");
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}
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}
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