805 lines
16 KiB
C
805 lines
16 KiB
C
/* This is a software floating point library which can be used instead of
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the floating point routines in libgcc1.c for targets without hardware
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floating point. */
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/* Copyright (C) 1994,1997 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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In addition to the permissions in the GNU General Public License, the
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Free Software Foundation gives you unlimited permission to link the
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compiled version of this file with other programs, and to distribute
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those programs without any restriction coming from the use of this
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file. (The General Public License restrictions do apply in other
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respects; for example, they cover modification of the file, and
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distribution when not linked into another program.)
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* As a special exception, if you link this library with other files,
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some of which are compiled with GCC, to produce an executable,
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this library does not by itself cause the resulting executable
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to be covered by the GNU General Public License.
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This exception does not however invalidate any other reasons why
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the executable file might be covered by the GNU General Public License. */
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/* This implements IEEE 754 format arithmetic, but does not provide a
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mechanism for setting the rounding mode, or for generating or handling
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exceptions.
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The original code by Steve Chamberlain, hacked by Mark Eichin and Jim
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Wilson, all of Cygnus Support. */
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#ifndef SIM_FPU_C
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#define SIM_FPU_C
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#include "sim-main.h"
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#include "sim-fpu.h"
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#include "sim-assert.h"
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#include <math.h>
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/* Floating point number is <SIGN:1><EXP:EXPBITS><FRAC:FRACBITS> */
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#define SP_NGARDS 7L
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#define SP_GARDROUND 0x3f
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#define SP_GARDMASK ((unsigned) 0x7f)
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#define SP_GARDMSB ((unsigned) 0x40)
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#define SP_EXPBITS 8
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#define SP_EXPBIAS 127
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#define SP_FRACBITS 23
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#define SP_EXPMAX ((unsigned) 0xff)
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#define SP_QUIET_NAN 0x100000L
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#define SP_FRAC_NBITS 32
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#define SP_FRACHIGH 0x80000000L
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#define SP_FRACHIGH2 0xc0000000L
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#define DP_NGARDS 8L
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#define DP_GARDROUND 0x7f
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#define DP_GARDMASK ((unsigned) 0xff)
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#define DP_GARDMSB ((unsigned) 0x80)
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#define DP_EXPBITS 11
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#define DP_EXPBIAS 1023
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#define DP_FRACBITS 52
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#define DP_EXPMAX ((unsigned) 0x7ff)
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#define DP_QUIET_NAN MSBIT64 (12) /* 0x0008000000000000LL */
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#define DP_FRAC_NBITS 64
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#define DP_FRACHIGH MSMASK64 (1) /* 0x8000000000000000LL */
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#define DP_FRACHIGH2 MSMASK64 (2) /* 0xc000000000000000LL */
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#define EXPMAX (is_double ? DP_EXPMAX : SP_EXPMAX)
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#define EXPBITS (is_double ? DP_EXPBITS : SP_EXPBITS)
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#define EXPBIAS (is_double ? DP_EXPBIAS : SP_EXPBIAS)
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#define FRACBITS (is_double ? DP_FRACBITS : SP_FRACBITS)
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#define NGARDS (is_double ? DP_NGARDS : (SP_NGARDS ))
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#define SIGNBIT ((unsigned64)1 << (EXPBITS + FRACBITS))
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#define FRAC_NBITS (is_double ? DP_FRAC_NBITS : SP_FRAC_NBITS)
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#define GARDMASK (is_double ? DP_GARDMASK : SP_GARDMASK)
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#define GARDMSB (is_double ? DP_GARDMSB : SP_GARDMSB)
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#define GARDROUND (is_double ? DP_GARDROUND : SP_GARDROUND)
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/* F_D_BITOFF is the number of bits offset between the MSB of the mantissa
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of a float and of a double. Assumes there are only two float types.
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(double::FRAC_BITS+double::NGARGS-(float::FRAC_BITS-float::NGARDS))
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*/
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#define F_D_BITOFF (is_double ? 0 : (52+8-(23+7)))
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#if 0
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#define (is_double ? DP_ : SP_)
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#endif
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#define NORMAL_EXPMIN (-(EXPBIAS)+1)
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#define IMPLICIT_1 ((unsigned64)1 << (FRACBITS+NGARDS))
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#define IMPLICIT_2 ((unsigned64)1 << (FRACBITS+1+NGARDS))
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#define MAX_SI_INT (is_double ? LSMASK64 (63) : LSMASK64 (31))
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#define MAX_USI_INT (is_double ? LSMASK64 (64) : LSMASK64 (32))
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typedef enum
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{
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sim_fpu_class_snan,
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sim_fpu_class_qnan,
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sim_fpu_class_zero,
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sim_fpu_class_number,
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sim_fpu_class_infinity,
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} sim_fpu_class;
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typedef struct _sim_ufpu {
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sim_fpu_class class;
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int normal_exp;
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int sign;
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unsigned64 fraction;
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union {
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double d;
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unsigned64 i;
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} val;
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} sim_ufpu;
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STATIC_INLINE_SIM_FPU (unsigned64)
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pack_fpu (const sim_ufpu *src, int is_double)
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{
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unsigned64 fraction;
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unsigned64 exp;
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int sign;
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switch (src->class)
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{
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default:
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/* create a NaN */
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case sim_fpu_class_qnan:
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case sim_fpu_class_snan:
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sign = 1; /* fixme - always a qNaN */
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exp = EXPMAX;
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fraction = src->fraction;
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break;
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case sim_fpu_class_infinity:
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sign = src->sign;
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exp = EXPMAX;
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fraction = 0;
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break;
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case sim_fpu_class_zero:
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sign = src->sign;
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exp = 0;
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fraction = 0;
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break;
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case sim_fpu_class_number:
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if (src->normal_exp < NORMAL_EXPMIN)
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{
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/* This number's exponent is too low to fit into the bits
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available in the number, so we'll store 0 in the exponent and
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shift the fraction to the right to make up for it. */
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int shift = NORMAL_EXPMIN - src->normal_exp;
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sign = src->sign;
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exp = 0;
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if (shift > (FRAC_NBITS - NGARDS))
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{
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/* No point shifting, since it's more that 64 out. */
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fraction = 0;
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}
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else
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{
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/* Shift by the value */
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fraction = src->fraction >> F_D_BITOFF;
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fraction >>= shift;
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fraction >>= NGARDS;
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}
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}
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else if (src->normal_exp > EXPBIAS)
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{
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/* Infinity */
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sign = src->sign;
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exp = EXPMAX;
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fraction = 0;
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}
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else
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{
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sign = src->sign;
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exp = (src->normal_exp + EXPBIAS);
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fraction = src->fraction >> F_D_BITOFF;
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/* IF the gard bits are the all zero, but the first, then we're
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half way between two numbers, choose the one which makes the
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lsb of the answer 0. */
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if ((fraction & GARDMASK) == GARDMSB)
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{
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if (fraction & (1 << NGARDS))
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fraction += GARDROUND + 1;
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}
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else
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{
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/* Add a one to the guards to round up */
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fraction += GARDROUND;
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}
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if (fraction >= IMPLICIT_2)
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{
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fraction >>= 1;
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exp += 1;
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}
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fraction >>= NGARDS;
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}
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}
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return ((sign ? SIGNBIT : 0)
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| (exp << FRACBITS)
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| LSMASKED64 (fraction, FRACBITS));
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}
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STATIC_INLINE_SIM_FPU (void)
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unpack_fpu (sim_ufpu *dst, unsigned64 s, int is_double)
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{
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unsigned64 fraction = LSMASKED64 (s, FRACBITS);
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unsigned exp = LSMASKED64 (s >> FRACBITS, EXPBITS);
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dst->sign = (s & SIGNBIT) != 0;
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if (exp == 0)
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{
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/* Hmm. Looks like 0 */
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if (fraction == 0)
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{
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/* tastes like zero */
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dst->class = sim_fpu_class_zero;
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}
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else
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{
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/* Zero exponent with non zero fraction - it's denormalized,
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so there isn't a leading implicit one - we'll shift it so
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it gets one. */
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dst->normal_exp = exp - EXPBIAS + 1;
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fraction <<= NGARDS;
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dst->class = sim_fpu_class_number;
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while (fraction < IMPLICIT_1)
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{
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fraction <<= 1;
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dst->normal_exp--;
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}
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dst->fraction = fraction << F_D_BITOFF;
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}
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}
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else if (exp == EXPMAX)
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{
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/* Huge exponent*/
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if (fraction == 0)
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{
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/* Attached to a zero fraction - means infinity */
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dst->class = sim_fpu_class_infinity;
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}
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else
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{
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/* Non zero fraction, means nan */
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if (dst->sign)
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{
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dst->class = sim_fpu_class_snan;
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}
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else
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{
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dst->class = sim_fpu_class_qnan;
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}
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/* Keep the fraction part as the nan number */
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dst->fraction = fraction << F_D_BITOFF;
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}
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}
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else
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{
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/* Nothing strange about this number */
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dst->normal_exp = exp - EXPBIAS;
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dst->class = sim_fpu_class_number;
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dst->fraction = ((fraction << NGARDS) | IMPLICIT_1) << F_D_BITOFF;
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}
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/* sanity checks */
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dst->val.i = -1;
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dst->val.i = pack_fpu (dst, 1);
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{
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if (is_double)
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{
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ASSERT (dst->val.i == s);
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}
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else
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{
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unsigned32 val = pack_fpu (dst, 0);
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unsigned32 org = s;
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ASSERT (val == org);
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}
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}
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}
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STATIC_INLINE_SIM_FPU (sim_fpu)
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ufpu2fpu (const sim_ufpu *d)
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{
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sim_fpu ans;
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ans.val.i = pack_fpu (d, 1);
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return ans;
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}
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STATIC_INLINE_SIM_FPU (sim_ufpu)
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fpu2ufpu (const sim_fpu *d)
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{
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sim_ufpu ans;
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unpack_fpu (&ans, d->val.i, 1);
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return ans;
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}
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#if 0
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STATIC_INLINE_SIM_FPU (int)
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is_ufpu_number (const sim_ufpu *d)
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{
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switch (d->class)
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{
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case sim_fpu_class_zero:
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case sim_fpu_class_number:
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return 1;
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default:
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return 0;
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}
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}
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#endif
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STATIC_INLINE_SIM_FPU (int)
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is_ufpu_nan (const sim_ufpu *d)
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{
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switch (d->class)
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{
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case sim_fpu_class_qnan:
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case sim_fpu_class_snan:
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return 1;
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default:
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return 0;
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}
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}
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STATIC_INLINE_SIM_FPU (int)
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is_ufpu_zero (const sim_ufpu *d)
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{
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switch (d->class)
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{
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case sim_fpu_class_zero:
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return 1;
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default:
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return 0;
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}
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}
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STATIC_INLINE_SIM_FPU (int)
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is_ufpu_inf (const sim_ufpu *d)
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{
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switch (d->class)
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{
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case sim_fpu_class_infinity:
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return 1;
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default:
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return 0;
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}
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}
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STATIC_INLINE_SIM_FPU (sim_fpu)
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fpu_nan (void)
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{
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sim_ufpu tmp;
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tmp.class = sim_fpu_class_snan;
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tmp.fraction = 0;
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tmp.sign = 1;
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tmp.normal_exp = 0;
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return ufpu2fpu (&tmp);
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}
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STATIC_INLINE_SIM_FPU (signed64)
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fpu2i (sim_fpu s, int is_double)
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{
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sim_ufpu a = fpu2ufpu (&s);
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unsigned64 tmp;
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if (is_ufpu_zero (&a))
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return 0;
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if (is_ufpu_nan (&a))
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return 0;
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/* get reasonable MAX_SI_INT... */
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if (is_ufpu_inf (&a))
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return a.sign ? MAX_SI_INT : (-MAX_SI_INT)-1;
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/* it is a number, but a small one */
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if (a.normal_exp < 0)
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return 0;
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if (a.normal_exp > (FRAC_NBITS - 2))
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return a.sign ? (-MAX_SI_INT)-1 : MAX_SI_INT;
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if (a.normal_exp > (FRACBITS + NGARDS + F_D_BITOFF))
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tmp = (a.fraction << (a.normal_exp - (FRACBITS + NGARDS)));
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else
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tmp = (a.fraction >> ((FRACBITS + NGARDS + F_D_BITOFF) - a.normal_exp));
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return a.sign ? (-tmp) : (tmp);
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}
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STATIC_INLINE_SIM_FPU (unsigned64)
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fpu2u (sim_fpu s, int is_double)
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{
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sim_ufpu a = fpu2ufpu (&s);
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unsigned64 tmp;
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if (is_ufpu_zero (&a))
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return 0;
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if (is_ufpu_nan (&a))
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return 0;
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/* get reasonable MAX_USI_INT... */
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if (is_ufpu_inf (&a))
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return a.sign ? MAX_USI_INT : 0;
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/* it is a negative number */
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if (a.sign)
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return 0;
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/* it is a number, but a small one */
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if (a.normal_exp < 0)
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return 0;
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if (a.normal_exp > (FRAC_NBITS - 1))
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return MAX_USI_INT;
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if (a.normal_exp > (FRACBITS + NGARDS + F_D_BITOFF))
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tmp = (a.fraction << (a.normal_exp - (FRACBITS + NGARDS + F_D_BITOFF)));
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else
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tmp = (a.fraction >> ((FRACBITS + NGARDS + F_D_BITOFF) - a.normal_exp));
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return tmp;
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}
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/* register <-> sim_fpu */
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INLINE_SIM_FPU (sim_fpu)
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sim_fpu_32to (unsigned32 s)
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{
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sim_ufpu tmp;
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unpack_fpu (&tmp, s, 0);
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return ufpu2fpu (&tmp);
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}
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INLINE_SIM_FPU (sim_fpu)
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sim_fpu_64to (unsigned64 s)
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{
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sim_fpu ans;
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ans.val.i = s;
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return ans;
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}
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INLINE_SIM_FPU (unsigned32)
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sim_fpu_to32 (sim_fpu l)
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{
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/* convert to single safely */
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sim_ufpu tmp = fpu2ufpu (&l);
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return pack_fpu (&tmp, 0);
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}
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INLINE_SIM_FPU (unsigned64)
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sim_fpu_to64 (sim_fpu s)
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{
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return s.val.i;
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}
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/* Arithmetic ops */
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INLINE_SIM_FPU (sim_fpu)
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sim_fpu_add (sim_fpu l,
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sim_fpu r)
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{
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sim_fpu ans;
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ans.val.d = l.val.d + r.val.d;
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return ans;
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}
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INLINE_SIM_FPU (sim_fpu)
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sim_fpu_sub (sim_fpu l,
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sim_fpu r)
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{
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sim_fpu ans;
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ans.val.d = l.val.d - r.val.d;
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return ans;
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}
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INLINE_SIM_FPU (sim_fpu)
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sim_fpu_mul (sim_fpu l,
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sim_fpu r)
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{
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sim_fpu ans;
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ans.val.d = l.val.d * r.val.d;
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return ans;
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}
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INLINE_SIM_FPU (sim_fpu)
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sim_fpu_div (sim_fpu l,
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sim_fpu r)
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{
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const int is_double = 1;
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sim_ufpu a = fpu2ufpu (&l);
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sim_ufpu b = fpu2ufpu (&r);
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unsigned64 bit;
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unsigned64 numerator;
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unsigned64 denominator;
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unsigned64 quotient;
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if (is_ufpu_nan (&a))
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{
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return ufpu2fpu (&a);
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}
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if (is_ufpu_nan (&b))
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{
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return ufpu2fpu (&b);
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}
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if (is_ufpu_inf (&a) || is_ufpu_zero (&a))
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{
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if (a.class == b.class)
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return fpu_nan ();
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return l;
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}
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a.sign = a.sign ^ b.sign;
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if (is_ufpu_inf (&b))
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{
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a.fraction = 0;
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a.normal_exp = 0;
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return ufpu2fpu (&a);
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}
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if (is_ufpu_zero (&b))
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{
|
|
a.class = sim_fpu_class_infinity;
|
|
return ufpu2fpu (&a);
|
|
}
|
|
|
|
/* Calculate the mantissa by multiplying both 64bit numbers to get a
|
|
128 bit number */
|
|
{
|
|
/* quotient =
|
|
( numerator / denominator) * 2^(numerator exponent - denominator exponent)
|
|
*/
|
|
|
|
a.normal_exp = a.normal_exp - b.normal_exp;
|
|
numerator = a.fraction;
|
|
denominator = b.fraction;
|
|
|
|
if (numerator < denominator)
|
|
{
|
|
/* Fraction will be less than 1.0 */
|
|
numerator *= 2;
|
|
a.normal_exp--;
|
|
}
|
|
bit = IMPLICIT_1;
|
|
quotient = 0;
|
|
/* ??? Does divide one bit at a time. Optimize. */
|
|
while (bit)
|
|
{
|
|
if (numerator >= denominator)
|
|
{
|
|
quotient |= bit;
|
|
numerator -= denominator;
|
|
}
|
|
bit >>= 1;
|
|
numerator *= 2;
|
|
}
|
|
|
|
if ((quotient & GARDMASK) == GARDMSB)
|
|
{
|
|
if (quotient & (1 << NGARDS))
|
|
{
|
|
/* half way, so round to even */
|
|
quotient += GARDROUND + 1;
|
|
}
|
|
else if (numerator)
|
|
{
|
|
/* but we really weren't half way, more bits exist */
|
|
quotient += GARDROUND + 1;
|
|
}
|
|
}
|
|
|
|
a.fraction = quotient;
|
|
return ufpu2fpu (&a);
|
|
}
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_inv (sim_fpu r)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = 1 / r.val.d;
|
|
return ans;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_sqrt (sim_fpu r)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = sqrt (r.val.d);
|
|
return ans;
|
|
}
|
|
|
|
|
|
/* int/long -> sim_fpu */
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_i32to (signed32 s)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = s;
|
|
return ans;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (signed32)
|
|
sim_fpu_to32i (sim_fpu s)
|
|
{
|
|
return fpu2i (s, 0);
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_u32to (unsigned32 s)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = s;
|
|
return ans;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (unsigned32)
|
|
sim_fpu_to32u (sim_fpu s)
|
|
{
|
|
return fpu2u (s, 0);
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_i64to (signed64 s)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = s;
|
|
return ans;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (signed64)
|
|
sim_fpu_to64i (sim_fpu s)
|
|
{
|
|
return fpu2i (s, 1);
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_u64to (unsigned64 s)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = s;
|
|
return ans;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (unsigned64)
|
|
sim_fpu_to64u (sim_fpu s)
|
|
{
|
|
return fpu2u (s, 1);
|
|
}
|
|
|
|
|
|
/* sim_fpu -> host format */
|
|
|
|
INLINE_SIM_FPU (float)
|
|
sim_fpu_2f (sim_fpu f)
|
|
{
|
|
return f.val.d;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (double)
|
|
sim_fpu_2d (sim_fpu s)
|
|
{
|
|
return s.val.d;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_f2 (float f)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = f;
|
|
return ans;
|
|
}
|
|
|
|
|
|
INLINE_SIM_FPU (sim_fpu)
|
|
sim_fpu_d2 (double d)
|
|
{
|
|
sim_fpu ans;
|
|
ans.val.d = d;
|
|
return ans;
|
|
}
|
|
|
|
|
|
/* General */
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_nan (sim_fpu d)
|
|
{
|
|
sim_ufpu tmp = fpu2ufpu (&d);
|
|
return is_ufpu_nan (&tmp);
|
|
}
|
|
|
|
|
|
/* Compare operators */
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_lt (sim_fpu l,
|
|
sim_fpu r)
|
|
{
|
|
sim_ufpu tl = fpu2ufpu (&l);
|
|
sim_ufpu tr = fpu2ufpu (&r);
|
|
if (!is_ufpu_nan (&tl) && !is_ufpu_nan (&tr))
|
|
return (l.val.d < r.val.d);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_le (sim_fpu l,
|
|
sim_fpu r)
|
|
{
|
|
sim_ufpu tl = fpu2ufpu (&l);
|
|
sim_ufpu tr = fpu2ufpu (&r);
|
|
if (!is_ufpu_nan (&tl) && !is_ufpu_nan (&tr))
|
|
return (l.val.d <= r.val.d);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_eq (sim_fpu l,
|
|
sim_fpu r)
|
|
{
|
|
sim_ufpu tl = fpu2ufpu (&l);
|
|
sim_ufpu tr = fpu2ufpu (&r);
|
|
if (!is_ufpu_nan (&tl) && !is_ufpu_nan (&tr))
|
|
return (l.val.d == r.val.d);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_ne (sim_fpu l,
|
|
sim_fpu r)
|
|
{
|
|
sim_ufpu tl = fpu2ufpu (&l);
|
|
sim_ufpu tr = fpu2ufpu (&r);
|
|
if (!is_ufpu_nan (&tl) && !is_ufpu_nan (&tr))
|
|
return (l.val.d != r.val.d);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_ge (sim_fpu l,
|
|
sim_fpu r)
|
|
{
|
|
sim_ufpu tl = fpu2ufpu (&l);
|
|
sim_ufpu tr = fpu2ufpu (&r);
|
|
if (!is_ufpu_nan (&tl) && !is_ufpu_nan (&tr))
|
|
return (l.val.d >= r.val.d);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
INLINE_SIM_FPU (int)
|
|
sim_fpu_is_gt (sim_fpu l,
|
|
sim_fpu r)
|
|
{
|
|
sim_ufpu tl = fpu2ufpu (&l);
|
|
sim_ufpu tr = fpu2ufpu (&r);
|
|
if (!is_ufpu_nan (&tl) && !is_ufpu_nan (&tr))
|
|
return (l.val.d > r.val.d);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
#endif
|