3184d3f9a5
* features/arm-with-m-vfp-d16.xml: New file. Describes Cortex-M with VFPv4-sp-d16 FPU register layout. * features/Makefile (WHICH): Add arm-with-m-vfp-d16. * features/arm-with-m-vfp-d16.c: New. Generated from above. * arm-tdep.c: Include arm-with-m-vfp-d16.c. (arm-register_g_packet_guesses): Add vfp-d16 guess. (_initialise_arm_tdep): Initialize arm-with-m-vfp-d16 tdesc.
53 lines
2.6 KiB
C
53 lines
2.6 KiB
C
/* THIS FILE IS GENERATED. Original: arm-with-m-vfp-d16.xml */
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#include "defs.h"
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#include "osabi.h"
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#include "target-descriptions.h"
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struct target_desc *tdesc_arm_with_m_vfp_d16;
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static void
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initialize_tdesc_arm_with_m_vfp_d16 (void)
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{
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struct target_desc *result = allocate_target_description ();
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struct tdesc_feature *feature;
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feature = tdesc_create_feature (result, "org.gnu.gdb.arm.m-profile");
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tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "sp", 13, 1, NULL, 32, "data_ptr");
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tdesc_create_reg (feature, "lr", 14, 1, NULL, 32, "int");
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tdesc_create_reg (feature, "pc", 15, 1, NULL, 32, "code_ptr");
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tdesc_create_reg (feature, "xpsr", 25, 1, NULL, 32, "int");
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feature = tdesc_create_feature (result, "org.gnu.gdb.arm.vfp");
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tdesc_create_reg (feature, "d0", 26, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d1", 27, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d2", 28, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d3", 29, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d4", 30, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d5", 31, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d6", 32, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d7", 33, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d8", 34, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d9", 35, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d10", 36, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d11", 37, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d12", 38, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d13", 39, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d14", 40, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "d15", 41, 1, NULL, 64, "ieee_double");
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tdesc_create_reg (feature, "fpscr", 42, 1, "float", 32, "int");
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tdesc_arm_with_m_vfp_d16 = result;
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}
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