1258 lines
23 KiB
C
1258 lines
23 KiB
C
#include <signal.h>
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#include "v850_sim.h"
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#include "simops.h"
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void
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OP_10760 ()
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{
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}
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void
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OP_C7C0 ()
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{
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}
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void
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OP_760 ()
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{
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}
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/* bv disp9 */
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void
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OP_580 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_OV) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bl disp9 */
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void
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OP_581 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_CY) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* be disp9 */
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void
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OP_582 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_Z) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bnh disp 9*/
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void
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OP_583 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bn disp9 */
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void
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OP_584 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_S) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* br disp9 */
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void
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OP_585 ()
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{
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unsigned int op0;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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State.pc += op0;
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}
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/* blt disp9 */
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void
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OP_586 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* ble disp9 */
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void
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OP_587 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((((psw & PSW_Z) != 0)
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|| (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bnv disp9 */
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void
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OP_588 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_OV) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bnl disp9 */
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void
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OP_589 ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_CY) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bne disp9 */
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void
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OP_58A ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_Z) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bh disp9 */
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void
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OP_58B ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bp disp9 */
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void
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OP_58C ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_S) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bsa disp9 */
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void
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OP_58D ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((psw & PSW_SAT) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bge disp9 */
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void
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OP_58E ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bgt disp9 */
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void
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OP_58F ()
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{
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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psw = State.psw;
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if ((((psw & PSW_Z) != 0)
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|| (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* jmp [reg1] */
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void
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OP_60 ()
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{
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/* interp.c will bump this by +2, so correct for it here. */
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State.pc = State.regs[OP[0]] - 2;
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}
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/* jarl disp22, reg */
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void
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OP_780 ()
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{
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unsigned int op0, opc;
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int temp;
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temp = OP[0];
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temp = (temp << 10) >> 10;
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op0 = temp;
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opc = State.pc;
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State.pc += temp;
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/* Gross. jarl X,r0 is really jr and doesn't save its result. */
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if (OP[1] != 0)
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State.regs[OP[1]] = opc + 4;
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}
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/* add reg, reg */
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void
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OP_1C0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* add sign_extend(imm5), reg */
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void
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OP_240 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0x1f);
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temp = (temp << 27) >> 27;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* addi sign_extend(imm16), reg, reg */
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void
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OP_600 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0xffff);
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temp = (temp << 16) >> 16;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* sub reg1, reg2 */
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void
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OP_1A0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op1 - op0;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* subr reg1, reg2 */
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void
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OP_180 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 - op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op1);
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ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* mulh reg1, reg2 */
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void
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OP_E0 ()
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{
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State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
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* (State.regs[OP[0]] & 0xffff));
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}
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/* mulh sign_extend(imm5), reg2
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Condition codes */
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void
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OP_2E0 ()
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{
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int value = OP[0];
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value = (value << 27) >> 27;
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State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
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}
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/* mulhi imm16, reg1, reg2 */
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void
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OP_6E0 ()
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{
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int value = OP[0];
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value = value & 0xffff;
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State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
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}
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/* divh reg1, reg2 */
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void
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OP_40 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = State.regs[OP[0]] & 0xffff;
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temp = (temp << 16) >> 16;
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op0 = temp;
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op1 = State.regs[OP[1]];
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if (op0 == 0xffffffff && op1 == 0x80000000)
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{
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result = 0x80000000;
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ov = 1;
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}
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else if (op0 != 0)
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{
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result = op1 / op0;
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ov = 0;
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}
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else
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ov = 1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (ov ? PSW_OV : 0));
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}
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/* cmp reg, reg */
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void
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OP_1E0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op1 - op0;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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/* Set condition codes. */
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* cmp sign_extend(imm5), reg */
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void
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OP_260 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = OP[0];
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temp = (temp << 27) >> 27;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op1 - op0;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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/* Set condition codes. */
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* setf cccc,reg2 */
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void
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OP_7E0 ()
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{
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/* Hack alert. We turn off a bit in op0 since we really only
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wanted 4 bits. */
|
|
unsigned int op0, psw, result;
|
|
|
|
op0 = OP[0] & 0xf;
|
|
psw = State.psw;
|
|
|
|
switch (op0)
|
|
{
|
|
case 0x0:
|
|
result = ((psw & PSW_OV) != 0);
|
|
break;
|
|
case 0x1:
|
|
result = ((psw & PSW_CY) != 0);
|
|
break;
|
|
case 0x2:
|
|
result = ((psw & PSW_Z) != 0);
|
|
break;
|
|
case 0x3:
|
|
result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
|
|
break;
|
|
case 0x4:
|
|
result = ((psw & PSW_S) != 0);
|
|
break;
|
|
case 0x5:
|
|
result = 1;
|
|
break;
|
|
case 0x6:
|
|
result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
|
|
break;
|
|
case 0x7:
|
|
result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
|
|
|| ((psw & PSW_Z) != 0)) != 0);
|
|
break;
|
|
case 0x8:
|
|
result = ((psw & PSW_OV) == 0);
|
|
break;
|
|
case 0x9:
|
|
result = ((psw & PSW_CY) == 0);
|
|
break;
|
|
case 0xa:
|
|
result = ((psw & PSW_Z) == 0);
|
|
break;
|
|
case 0xb:
|
|
result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
|
|
break;
|
|
case 0xc:
|
|
result = ((psw & PSW_S) == 0);
|
|
break;
|
|
case 0xd:
|
|
result = ((psw & PSW_SAT) != 0);
|
|
break;
|
|
case 0xe:
|
|
result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
|
|
break;
|
|
case 0xf:
|
|
result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
|
|
|| ((psw & PSW_Z) != 0)) == 0);
|
|
break;
|
|
}
|
|
|
|
State.regs[OP[1]] = result;
|
|
}
|
|
|
|
/* satadd reg,reg */
|
|
void
|
|
OP_C0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 + op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < op0 || result < op1);
|
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && (op0 & 0x80000000))
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* satadd sign_extend(imm5), reg */
|
|
void
|
|
OP_220 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
int temp;
|
|
|
|
/* Compute the result. */
|
|
temp = (OP[0] & 0x1f);
|
|
temp = (temp << 27) >> 27;
|
|
op0 = temp;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 + op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < op0 || result < op1);
|
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && (op0 & 0x80000000))
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* satsub reg1, reg2 */
|
|
void
|
|
OP_A0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 - op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < -op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && (op1 & 0x80000000))
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* satsubi sign_extend(imm16), reg */
|
|
void
|
|
OP_660 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
int temp;
|
|
|
|
/* Compute the result. */
|
|
temp = (OP[0] & 0xffff);
|
|
temp = (temp << 16) >> 16;
|
|
op0 = temp;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 - op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < -op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && (op1 & 0x80000000))
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
void
|
|
OP_80 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 - op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < -op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && (op0 & 0x80000000))
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* tst reg,reg */
|
|
void
|
|
OP_160 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 & op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the condition codes. */
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
void
|
|
OP_10720 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_720 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_87C0 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_300 ()
|
|
{
|
|
}
|
|
|
|
/* mov reg, reg */
|
|
void
|
|
OP_0 ()
|
|
{
|
|
State.regs[OP[1]] = State.regs[OP[0]];
|
|
}
|
|
|
|
/* mov sign_extend(imm5), reg */
|
|
void
|
|
OP_200 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value << 27) >> 27;
|
|
State.regs[OP[1]] = value;
|
|
}
|
|
|
|
/* movea sign_extend(imm16), reg, reg */
|
|
|
|
void
|
|
OP_620 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value << 16) >> 16;
|
|
|
|
State.regs[OP[2]] = State.regs[OP[1]] + value;
|
|
}
|
|
|
|
/* movhi imm16, reg, reg */
|
|
void
|
|
OP_640 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value & 0xffff) << 16;
|
|
|
|
State.regs[OP[2]] = State.regs[OP[1]] + value;
|
|
}
|
|
|
|
void
|
|
OP_7C0 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_1687E0 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_740 ()
|
|
{
|
|
}
|
|
|
|
/* sar zero_extend(imm5),reg1 */
|
|
void
|
|
OP_2A0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = (signed)op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* sar reg1, reg2 */
|
|
void
|
|
OP_A007E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = State.regs[OP[0]] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = (signed)op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shl zero_extend(imm5),reg1 */
|
|
void
|
|
OP_2C0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 << op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (32 - op0)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shl reg1, reg2 */
|
|
void
|
|
OP_C007E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = State.regs[OP[0]] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 << op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (32 - op0)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shr zero_extend(imm5),reg1 */
|
|
void
|
|
OP_280 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shr reg1, reg2 */
|
|
void
|
|
OP_8007E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = State.regs[OP[0]] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
void
|
|
OP_500 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_47C0 ()
|
|
{
|
|
}
|
|
|
|
/* or reg, reg */
|
|
void
|
|
OP_100 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 | op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* ori zero_extend(imm16), reg, reg */
|
|
void
|
|
OP_680 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0xffff;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 | op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[2]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* and reg, reg */
|
|
void
|
|
OP_140 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 & op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* andi zero_extend(imm16), reg, reg */
|
|
void
|
|
OP_6C0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0xffff;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 & op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[2]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= (z ? PSW_Z : 0);
|
|
}
|
|
|
|
/* xor reg, reg */
|
|
void
|
|
OP_120 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 ^ op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* xori zero_extend(imm16), reg, reg */
|
|
void
|
|
OP_6A0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0xffff;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 ^ op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[2]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* not reg1, reg2 */
|
|
void
|
|
OP_20 ()
|
|
{
|
|
unsigned int op0, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
result = ~op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
void
|
|
OP_480 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_380 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_501 ()
|
|
{
|
|
}
|
|
|
|
/* di */
|
|
void
|
|
OP_16007E0 ()
|
|
{
|
|
State.psw |= PSW_ID;
|
|
}
|
|
|
|
/* ei */
|
|
void
|
|
OP_16087E0 ()
|
|
{
|
|
State.psw &= ~PSW_ID;
|
|
}
|
|
|
|
/* halt, not supported */
|
|
void
|
|
OP_12007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* reti, not supported */
|
|
void
|
|
OP_14007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* trap, not supportd */
|
|
void
|
|
OP_10007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* ldsr, not supported */
|
|
void
|
|
OP_2007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* stsr, not supported */
|
|
void
|
|
OP_4007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
void
|
|
OP_400 ()
|
|
{
|
|
}
|
|
|
|
void
|
|
OP_700 ()
|
|
{
|
|
}
|
|
|