894 lines
25 KiB
C
894 lines
25 KiB
C
/* tc-tic80.c -- Assemble for the TI TMS320C80 (MV)
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Copyright 1996, 1997, 2000, 2001, 2002, 2005
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#include "as.h"
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#include "safe-ctype.h"
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#include "opcode/tic80.h"
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#define internal_error(what) \
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as_fatal (_("internal error:%s:%d: %s\n"), __FILE__, __LINE__, what)
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#define internal_error_a(what,arg) \
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as_fatal (_("internal error:%s:%d: %s %ld\n"), __FILE__, __LINE__, what, arg)
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/* Generic assembler global variables which must be defined by all
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targets. */
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/* Characters which always start a comment. */
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const char comment_chars[] = ";";
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/* Characters which start a comment at the beginning of a line. */
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const char line_comment_chars[] = ";*#";
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/* Characters which may be used to separate multiple commands on a single
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line. The semicolon is such a character by default and should not be
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explicitly listed. */
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const char line_separator_chars[] = "";
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/* Characters which are used to indicate an exponent in a floating
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point number. */
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const char EXP_CHARS[] = "eE";
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/* Characters which mean that a number is a floating point constant,
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as in 0f1.0. */
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const char FLT_CHARS[] = "fF";
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/* This table describes all the machine specific pseudo-ops the assembler
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has to support. The fields are:
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pseudo-op name without dot
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function to call to execute this pseudo-op
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integer arg to pass to the function */
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const pseudo_typeS md_pseudo_table[] =
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{
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{ "align", s_align_bytes, 4 }, /* Do byte alignment, default is a 4 byte boundary. */
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{ "word", cons, 4 }, /* FIXME: Should this be machine independent? */
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{ "bss", s_lcomm_bytes, 1 },
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{ "sect", obj_coff_section, 0}, /* For compatibility with TI tools. */
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{ "section", obj_coff_section, 0}, /* Standard COFF .section pseudo-op. */
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{ NULL, NULL, 0 }
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};
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/* Opcode hash table. */
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static struct hash_control *tic80_hash;
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/* Replace short PC relative instructions with long form when
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necessary. Currently this is off by default or when given the
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-no-relax option. Turning it on by using the -relax option forces
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all PC relative instructions to use the long form, which is why it
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is currently not the default. */
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static int tic80_relax = 0;
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int
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md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
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segT segment_type ATTRIBUTE_UNUSED)
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{
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internal_error (_("Relaxation is a luxury we can't afford"));
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return -1;
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}
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/* We have no need to default values of symbols. */
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symbolS *
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md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
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{
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return NULL;
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}
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/* Turn a string in input_line_pointer into a floating point constant
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of type TYPE, and store the appropriate bytes in *LITP. The number
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of LITTLENUMS emitted is stored in *SIZEP. An error message is
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returned, or NULL on OK. */
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#define MAX_LITTLENUMS 4
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char *
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md_atof (int type, char *litP, int *sizeP)
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{
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int prec;
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LITTLENUM_TYPE words[MAX_LITTLENUMS];
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LITTLENUM_TYPE *wordP;
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char *t;
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switch (type)
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{
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case 'f':
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case 'F':
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case 's':
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case 'S':
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prec = 2;
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break;
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case 'd':
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case 'D':
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case 'r':
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case 'R':
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prec = 4;
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break;
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default:
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*sizeP = 0;
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return _("bad call to md_atof ()");
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}
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t = atof_ieee (input_line_pointer, type, words);
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if (t)
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input_line_pointer = t;
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*sizeP = prec * sizeof (LITTLENUM_TYPE);
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for (wordP = words; prec--;)
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{
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md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
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litP += sizeof (LITTLENUM_TYPE);
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}
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return NULL;
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}
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/* Check to see if the constant value in NUM will fit in a field of
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width BITS if it has flags FLAGS. */
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static int
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const_overflow (unsigned long num, int bits, int flags)
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{
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long min, max;
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int retval = 0;
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/* Only need to check fields less than 32 bits wide. */
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if (bits >= 32)
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return retval;
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if (flags & TIC80_OPERAND_SIGNED)
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{
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max = (1 << (bits - 1)) - 1;
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min = - (1 << (bits - 1));
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retval = (long) num > max || (long) num < min;
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}
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else
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{
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max = (1 << bits) - 1;
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retval = num > (unsigned long) max;
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}
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return retval;
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}
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/* get_operands () parses a string of operands and fills in a passed
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array of expressions in EXP.
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Note that we use O_absent expressions to record additional information
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about the previous non-O_absent expression, such as ":m" or ":s"
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modifiers or register numbers enclosed in parens like "(r10)".
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Returns the number of expressions that were placed in EXP. */
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static int
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get_operands (expressionS exp[])
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{
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char *p = input_line_pointer;
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int numexp = 0;
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int parens = 0;
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while (*p)
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{
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/* Skip leading whitespace. */
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while (*p == ' ' || *p == '\t' || *p == ',')
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p++;
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/* Check to see if we have any operands left to parse. */
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if (*p == 0 || *p == '\n' || *p == '\r')
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break;
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/* Notice scaling or direct memory operand modifiers and save them in
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an O_absent expression after the expression that they modify. */
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if (*p == ':')
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{
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p++;
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exp[numexp].X_op = O_absent;
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if (*p == 'm')
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{
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p++;
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/* This is a ":m" modifier. */
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exp[numexp].X_add_number = TIC80_OPERAND_M_SI | TIC80_OPERAND_M_LI;
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}
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else if (*p == 's')
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{
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p++;
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/* This is a ":s" modifier. */
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exp[numexp].X_add_number = TIC80_OPERAND_SCALED;
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}
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else
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as_bad (_("':' not followed by 'm' or 's'"));
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numexp++;
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continue;
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}
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/* Handle leading '(' on operands that use them, by recording that we
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have entered a paren nesting level and then continuing. We complain
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about multiple nesting. */
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if (*p == '(')
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{
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if (++parens != 1)
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as_bad (_("paren nesting"));
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p++;
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continue;
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}
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/* Handle trailing ')' on operands that use them, by reducing the
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nesting level and then continuing. We complain if there were too
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many closures. */
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if (*p == ')')
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{
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/* Record that we have left a paren group and continue. */
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if (--parens < 0)
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as_bad (_("mismatched parenthesis"));
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p++;
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continue;
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}
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/* Begin operand parsing at the current scan point. */
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input_line_pointer = p;
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expression (&exp[numexp]);
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if (exp[numexp].X_op == O_illegal)
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as_bad (_("illegal operand"));
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else if (exp[numexp].X_op == O_absent)
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as_bad (_("missing operand"));
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numexp++;
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p = input_line_pointer;
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}
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if (parens)
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{
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exp[numexp].X_op = O_absent;
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exp[numexp++].X_add_number = TIC80_OPERAND_PARENS;
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}
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/* Mark the end of the valid operands with an illegal expression. */
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exp[numexp].X_op = O_illegal;
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return numexp;
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}
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/* find_opcode() gets a pointer to the entry in the opcode table that
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matches the instruction being assembled, or returns NULL if no such match
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is found.
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First it parses all the operands and save them as expressions. Note that
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we use O_absent expressions to record additional information about the
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previous non-O_absent expression, such as ":m" or ":s" modifiers or
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register numbers enclosed in parens like "(r10)".
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It then looks at all opcodes with the same name and uses the operands to
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choose the correct opcode. */
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static struct tic80_opcode *
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find_opcode (struct tic80_opcode *opcode, expressionS myops[])
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{
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int numexp; /* Number of expressions from parsing operands. */
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int expi; /* Index of current expression to match. */
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int opi; /* Index of current operand to match. */
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int match = 0; /* Set to 1 when an operand match is found. */
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struct tic80_opcode *opc = opcode; /* Pointer to current opcode table entry. */
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const struct tic80_opcode *end; /* Pointer to end of opcode table. */
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/* First parse all the operands so we only have to do it once. There may
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be more expressions generated than there are operands. */
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numexp = get_operands (myops);
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/* For each opcode with the same name, try to match it against the parsed
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operands. */
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end = tic80_opcodes + tic80_num_opcodes;
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while (!match && (opc < end) && (strcmp (opc->name, opcode->name) == 0))
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{
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/* Start off assuming a match. If we find a mismatch, then this is
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reset and the operand/expr matching loop terminates with match
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equal to zero, which allows us to try the next opcode. */
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match = 1;
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/* For each expression, try to match it against the current operand
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for the current opcode. Upon any mismatch, we abandon further
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matching for the current opcode table entry. */
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for (expi = 0, opi = -1; (expi < numexp) && match; expi++)
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{
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int bits, flags, X_op, num;
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X_op = myops[expi].X_op;
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num = myops[expi].X_add_number;
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/* The O_absent expressions apply to the same operand as the most
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recent non O_absent expression. So only increment the operand
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index when the current expression is not one of these special
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expressions. */
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if (X_op != O_absent)
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opi++;
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flags = tic80_operands[opc->operands[opi]].flags;
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bits = tic80_operands[opc->operands[opi]].bits;
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switch (X_op)
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{
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case O_register:
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/* Also check that registers that are supposed to be
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even actually are even. */
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if (((flags & TIC80_OPERAND_GPR) != (num & TIC80_OPERAND_GPR)) ||
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((flags & TIC80_OPERAND_FPA) != (num & TIC80_OPERAND_FPA)) ||
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((flags & TIC80_OPERAND_CR) != (num & TIC80_OPERAND_CR)) ||
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((flags & TIC80_OPERAND_EVEN) && (num & 1)) ||
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const_overflow (num & ~TIC80_OPERAND_MASK, bits, flags))
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match = 0;
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break;
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case O_constant:
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if ((flags & TIC80_OPERAND_ENDMASK) && (num == 32))
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/* Endmask values of 0 and 32 give identical
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results. */
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num = 0;
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if ((flags & (TIC80_OPERAND_FPA | TIC80_OPERAND_GPR)) ||
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const_overflow (num, bits, flags))
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match = 0;
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break;
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case O_symbol:
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if ((bits < 32) && (flags & TIC80_OPERAND_PCREL)
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&& !tic80_relax)
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{
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/* The default is to prefer the short form of PC
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relative relocations. This is the only form that
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the TI assembler supports. If the -relax option
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is given, we never use the short forms.
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FIXME: Should be able to choose "best-fit". */
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}
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else if ((bits == 32))
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{
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/* The default is to prefer the long form of base
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relative relocations. This is the only form that
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the TI assembler supports. If the -no-relax
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option is given, we always use the long form of
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PC relative relocations.
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FIXME: Should be able to choose "best-fit". */
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}
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else
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{
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/* Symbols that don't match one of the above cases are
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rejected as an operand. */
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match = 0;
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}
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break;
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case O_absent:
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/* If this is an O_absent expression, then it may be an
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expression that supplies additional information about
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the operand, such as ":m" or ":s" modifiers. Check to
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see that the operand matches this requirement. */
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if (!((num & flags & TIC80_OPERAND_M_SI)
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|| (num & flags & TIC80_OPERAND_M_LI)
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|| (num & flags & TIC80_OPERAND_SCALED)))
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match = 0;
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break;
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case O_big:
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if ((num > 0) || !(flags & TIC80_OPERAND_FLOAT))
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match = 0;
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break;
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case O_illegal:
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case O_symbol_rva:
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case O_uminus:
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case O_bit_not:
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case O_logical_not:
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case O_multiply:
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case O_divide:
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case O_modulus:
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case O_left_shift:
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case O_right_shift:
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case O_bit_inclusive_or:
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case O_bit_or_not:
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case O_bit_exclusive_or:
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case O_bit_and:
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case O_add:
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case O_subtract:
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case O_eq:
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case O_ne:
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case O_lt:
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case O_le:
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case O_ge:
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case O_gt:
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case O_logical_and:
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case O_logical_or:
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case O_max:
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default:
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internal_error_a (_("unhandled expression type"), (long) X_op);
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}
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}
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if (!match)
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opc++;
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}
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return match ? opc : NULL;
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}
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/* build_insn takes a pointer to the opcode entry in the opcode table
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and the array of operand expressions and writes out the instruction.
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Note that the opcode word and extended word may be written to different
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frags, with the opcode at the end of one frag and the extension at the
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beginning of the next. */
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static void
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build_insn (struct tic80_opcode *opcode, expressionS *opers)
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{
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int expi; /* Index of current expression to match. */
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int opi; /* Index of current operand to match. */
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unsigned long insn[2]; /* Instruction and long immediate (if any). */
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char *f; /* Pointer to frag location for insn[0]. */
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fragS *ffrag; /* Frag containing location f. */
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char *fx = NULL; /* Pointer to frag location for insn[1]. */
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fragS *fxfrag; /* Frag containing location fx. */
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/* Start with the raw opcode bits from the opcode table. */
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insn[0] = opcode->opcode;
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insn[1] = 0;
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/* We are going to insert at least one 32 bit opcode so get the
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frag now. */
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f = frag_more (4);
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ffrag = frag_now;
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/* For each operand expression, insert the appropriate bits into the
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instruction. */
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for (expi = 0, opi = -1; opers[expi].X_op != O_illegal; expi++)
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{
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int bits, shift, flags, X_op, num;
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X_op = opers[expi].X_op;
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num = opers[expi].X_add_number;
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/* The O_absent expressions apply to the same operand as the most
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recent non O_absent expression. So only increment the operand
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index when the current expression is not one of these special
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expressions. */
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if (X_op != O_absent)
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opi++;
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flags = tic80_operands[opcode->operands[opi]].flags;
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bits = tic80_operands[opcode->operands[opi]].bits;
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shift = tic80_operands[opcode->operands[opi]].shift;
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switch (X_op)
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{
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case O_register:
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num &= ~TIC80_OPERAND_MASK;
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insn[0] = insn[0] | (num << shift);
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break;
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case O_constant:
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if ((flags & TIC80_OPERAND_ENDMASK) && (num == 32))
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/* Endmask values of 0 and 32 give identical results. */
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num = 0;
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else if ((flags & TIC80_OPERAND_BITNUM))
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/* BITNUM values are stored in one's complement form. */
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num = (~num & 0x1F);
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/* Mask off upper bits, just it case it is signed and is
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negative. */
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if (bits < 32)
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{
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num &= (1 << bits) - 1;
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insn[0] = insn[0] | (num << shift);
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}
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else
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{
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fx = frag_more (4);
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fxfrag = frag_now;
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insn[1] = num;
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}
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break;
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case O_symbol:
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if (bits == 32)
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{
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fx = frag_more (4);
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fxfrag = frag_now;
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insn[1] = 0;
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if (flags & TIC80_OPERAND_PCREL)
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fix_new_exp (fxfrag, fx - (fxfrag->fr_literal),
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4, &opers[expi], 1, R_MPPCR);
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else
|
||
fix_new_exp (fxfrag, fx - (fxfrag->fr_literal),
|
||
4, &opers[expi], 0, R_RELLONGX);
|
||
}
|
||
else if (flags & TIC80_OPERAND_PCREL)
|
||
fix_new_exp (ffrag, f - (ffrag->fr_literal),
|
||
4, /* FIXME! how is this used? */
|
||
&opers[expi], 1, R_MPPCR15W);
|
||
else
|
||
internal_error (_("symbol reloc that is not PC relative or 32 bits"));
|
||
break;
|
||
|
||
case O_absent:
|
||
/* Each O_absent expression can indicate exactly one
|
||
possible modifier. */
|
||
if ((num & TIC80_OPERAND_M_SI)
|
||
&& (flags & TIC80_OPERAND_M_SI))
|
||
insn[0] = insn[0] | (1 << 17);
|
||
else if ((num & TIC80_OPERAND_M_LI)
|
||
&& (flags & TIC80_OPERAND_M_LI))
|
||
insn[0] = insn[0] | (1 << 15);
|
||
else if ((num & TIC80_OPERAND_SCALED)
|
||
&& (flags & TIC80_OPERAND_SCALED))
|
||
insn[0] = insn[0] | (1 << 11);
|
||
else if ((num & TIC80_OPERAND_PARENS)
|
||
&& (flags & TIC80_OPERAND_PARENS))
|
||
/* No code to generate, just accept and discard this
|
||
expression. */
|
||
;
|
||
else
|
||
internal_error_a (_("unhandled operand modifier"),
|
||
(long) opers[expi].X_add_number);
|
||
break;
|
||
|
||
case O_big:
|
||
fx = frag_more (4);
|
||
fxfrag = frag_now;
|
||
|
||
{
|
||
int precision = 2;
|
||
long exponent_bits = 8L;
|
||
LITTLENUM_TYPE words[2];
|
||
|
||
/* Value is still in generic_floating_point_number. */
|
||
gen_to_words (words, precision, exponent_bits);
|
||
insn[1] = (words[0] << 16) | words[1];
|
||
}
|
||
break;
|
||
|
||
case O_illegal:
|
||
case O_symbol_rva:
|
||
case O_uminus:
|
||
case O_bit_not:
|
||
case O_logical_not:
|
||
case O_multiply:
|
||
case O_divide:
|
||
case O_modulus:
|
||
case O_left_shift:
|
||
case O_right_shift:
|
||
case O_bit_inclusive_or:
|
||
case O_bit_or_not:
|
||
case O_bit_exclusive_or:
|
||
case O_bit_and:
|
||
case O_add:
|
||
case O_subtract:
|
||
case O_eq:
|
||
case O_ne:
|
||
case O_lt:
|
||
case O_le:
|
||
case O_ge:
|
||
case O_gt:
|
||
case O_logical_and:
|
||
case O_logical_or:
|
||
case O_max:
|
||
default:
|
||
internal_error_a (_("unhandled expression"), (long) X_op);
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* Write out the instruction, either 4 or 8 bytes. */
|
||
|
||
md_number_to_chars (f, insn[0], 4);
|
||
if (fx != NULL)
|
||
md_number_to_chars (fx, insn[1], 4);
|
||
}
|
||
|
||
/* This is the main entry point for the machine-dependent assembler. Gas
|
||
calls this function for each input line which does not contain a
|
||
pseudoop.
|
||
|
||
STR points to a NULL terminated machine dependent instruction. This
|
||
function is supposed to emit the frags/bytes it assembles to. */
|
||
|
||
void
|
||
md_assemble (char *str)
|
||
{
|
||
char *scan;
|
||
char *input_line_save;
|
||
struct tic80_opcode *opcode;
|
||
expressionS myops[16];
|
||
|
||
/* Ensure there is something there to assemble. */
|
||
assert (str);
|
||
|
||
/* Drop any leading whitespace. */
|
||
while (ISSPACE (*str))
|
||
str++;
|
||
|
||
/* Isolate the mnemonic from the rest of the string by finding the first
|
||
whitespace character and zapping it to a null byte. */
|
||
for (scan = str; *scan != '\000' && !ISSPACE (*scan); scan++)
|
||
;
|
||
|
||
if (*scan != '\000')
|
||
*scan++ = '\000';
|
||
|
||
/* Try to find this mnemonic in the hash table. */
|
||
if ((opcode = (struct tic80_opcode *) hash_find (tic80_hash, str)) == NULL)
|
||
{
|
||
as_bad (_("Invalid mnemonic: '%s'"), str);
|
||
return;
|
||
}
|
||
|
||
str = scan;
|
||
while (ISSPACE (*scan))
|
||
scan++;
|
||
|
||
input_line_save = input_line_pointer;
|
||
input_line_pointer = str;
|
||
|
||
opcode = find_opcode (opcode, myops);
|
||
if (opcode == NULL)
|
||
as_bad (_("Invalid operands: '%s'"), input_line_save);
|
||
|
||
input_line_pointer = input_line_save;
|
||
build_insn (opcode, myops);
|
||
}
|
||
|
||
/* This function is called once at the start of assembly, after the command
|
||
line arguments have been parsed and all the machine independent
|
||
initializations have been completed.
|
||
|
||
It should set up all the tables, etc., that the machine dependent part of
|
||
the assembler will need. */
|
||
|
||
void
|
||
md_begin (void)
|
||
{
|
||
char *prev_name = "";
|
||
register const struct tic80_opcode *op;
|
||
register const struct tic80_opcode *op_end;
|
||
const struct predefined_symbol *pdsp;
|
||
extern int coff_flags; /* Defined in obj-coff.c */
|
||
|
||
/* Set F_AR32WR in coff_flags, which will end up in the file header
|
||
f_flags field. */
|
||
|
||
coff_flags |= F_AR32WR; /* TIc80 is 32 bit little endian. */
|
||
|
||
/* Insert unique names into hash table. The TIc80 instruction set
|
||
has many identical opcode names that have different opcodes based
|
||
on the operands. This hash table then provides a quick index to
|
||
the first opcode with a particular name in the opcode table. */
|
||
|
||
tic80_hash = hash_new ();
|
||
op_end = tic80_opcodes + tic80_num_opcodes;
|
||
for (op = tic80_opcodes; op < op_end; op++)
|
||
{
|
||
if (strcmp (prev_name, op->name) != 0)
|
||
{
|
||
prev_name = (char *) op->name;
|
||
hash_insert (tic80_hash, op->name, (char *) op);
|
||
}
|
||
}
|
||
|
||
/* Insert the predefined symbols into the symbol table. We use
|
||
symbol_create rather than symbol_new so that these symbols don't
|
||
end up in the object files' symbol table. Note that the values
|
||
of the predefined symbols include some upper bits that
|
||
distinguish the type of the symbol (register, bitnum, condition
|
||
code, etc) and these bits must be masked away before actually
|
||
inserting the values into the instruction stream. For registers
|
||
we put these bits in the symbol table since we use them later and
|
||
there is no question that they aren't part of the register
|
||
number. For constants we can't do that since the constant can be
|
||
any value, so they are masked off before putting them into the
|
||
symbol table. */
|
||
|
||
pdsp = NULL;
|
||
while ((pdsp = tic80_next_predefined_symbol (pdsp)) != NULL)
|
||
{
|
||
segT segment;
|
||
valueT valu;
|
||
int symtype;
|
||
|
||
symtype = PDS_VALUE (pdsp) & TIC80_OPERAND_MASK;
|
||
switch (symtype)
|
||
{
|
||
case TIC80_OPERAND_GPR:
|
||
case TIC80_OPERAND_FPA:
|
||
case TIC80_OPERAND_CR:
|
||
segment = reg_section;
|
||
valu = PDS_VALUE (pdsp);
|
||
break;
|
||
case TIC80_OPERAND_CC:
|
||
case TIC80_OPERAND_BITNUM:
|
||
segment = absolute_section;
|
||
valu = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
|
||
break;
|
||
default:
|
||
internal_error_a (_("unhandled predefined symbol bits"),
|
||
(long) symtype);
|
||
break;
|
||
}
|
||
symbol_table_insert (symbol_create (PDS_NAME (pdsp), segment, valu,
|
||
&zero_address_frag));
|
||
}
|
||
}
|
||
|
||
/* The assembler adds md_shortopts to the string passed to getopt. */
|
||
|
||
const char *md_shortopts = "";
|
||
|
||
/* The assembler adds md_longopts to the machine independent long options
|
||
that are passed to getopt. */
|
||
|
||
struct option md_longopts[] =
|
||
{
|
||
#define OPTION_RELAX (OPTION_MD_BASE)
|
||
{"relax", no_argument, NULL, OPTION_RELAX},
|
||
|
||
#define OPTION_NO_RELAX (OPTION_RELAX + 1)
|
||
{"no-relax", no_argument, NULL, OPTION_NO_RELAX},
|
||
|
||
{NULL, no_argument, NULL, 0}
|
||
};
|
||
|
||
size_t md_longopts_size = sizeof (md_longopts);
|
||
|
||
/* The md_parse_option function will be called whenever getopt returns an
|
||
unrecognized code, presumably indicating a special code value which
|
||
appears in md_longopts for machine specific command line options. */
|
||
|
||
int
|
||
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
|
||
{
|
||
switch (c)
|
||
{
|
||
case OPTION_RELAX:
|
||
tic80_relax = 1;
|
||
break;
|
||
case OPTION_NO_RELAX:
|
||
tic80_relax = 0;
|
||
break;
|
||
default:
|
||
return 0;
|
||
}
|
||
return 1;
|
||
}
|
||
|
||
/* The md_show_usage function will be called whenever a usage message is
|
||
printed. It should print a description of the machine specific options
|
||
found in md_longopts. */
|
||
|
||
void
|
||
md_show_usage (FILE *stream)
|
||
{
|
||
fprintf (stream, "\
|
||
TIc80 options:\n\
|
||
-relax alter PC relative branch instructions to use long form when needed\n\
|
||
-no-relax always use short PC relative branch instructions, error on overflow\n");
|
||
}
|
||
|
||
/* Attempt to simplify or even eliminate a fixup. The return value is
|
||
ignored; perhaps it was once meaningful, but now it is historical.
|
||
To indicate that a fixup has been eliminated, set fixP->fx_done. */
|
||
|
||
void
|
||
md_apply_fix3 (fixS *fixP, valueT * valP, segT seg ATTRIBUTE_UNUSED)
|
||
{
|
||
long val = * (long *) valP;
|
||
char *dest = fixP->fx_frag->fr_literal + fixP->fx_where;
|
||
int overflow;
|
||
|
||
switch (fixP->fx_r_type)
|
||
{
|
||
case R_RELLONGX:
|
||
md_number_to_chars (dest, (valueT) val, 4);
|
||
break;
|
||
case R_MPPCR:
|
||
val >>= 2;
|
||
val += 1; /* Target address computed from inst start. */
|
||
md_number_to_chars (dest, (valueT) val, 4);
|
||
break;
|
||
case R_MPPCR15W:
|
||
overflow = (val < -65536L) || (val > 65532L);
|
||
if (overflow)
|
||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||
_("PC offset 0x%lx outside range 0x%lx-0x%lx"),
|
||
val, -65536L, 65532L);
|
||
else
|
||
{
|
||
val >>= 2;
|
||
*dest++ = val & 0xFF;
|
||
val >>= 8;
|
||
*dest = (*dest & 0x80) | (val & 0x7F);
|
||
}
|
||
break;
|
||
|
||
case R_ABS:
|
||
md_number_to_chars (dest, (valueT) val, fixP->fx_size);
|
||
break;
|
||
|
||
default:
|
||
internal_error_a (_("unhandled relocation type in fixup"),
|
||
(long) fixP->fx_r_type);
|
||
break;
|
||
}
|
||
|
||
if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
|
||
fixP->fx_done = 1;
|
||
}
|
||
|
||
/* Functions concerning relocs. */
|
||
|
||
/* The location from which a PC relative jump should be calculated,
|
||
given a PC relative reloc.
|
||
|
||
For the TIc80, this is the address of the 32 bit opcode containing
|
||
the PC relative field. */
|
||
|
||
long
|
||
md_pcrel_from (fixS *fixP)
|
||
{
|
||
return (fixP->fx_frag->fr_address + fixP->fx_where);
|
||
}
|
||
|
||
/* Called after relax() is finished.
|
||
In: Address of frag.
|
||
fr_type == rs_machine_dependent.
|
||
fr_subtype is what the address relaxed to.
|
||
|
||
Out: Any fixSs and constants are set up.
|
||
Caller will turn frag into a ".space 0". */
|
||
|
||
void
|
||
md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
|
||
segT seg ATTRIBUTE_UNUSED,
|
||
fragS *fragP ATTRIBUTE_UNUSED)
|
||
{
|
||
internal_error (_("md_convert_frag() not implemented yet"));
|
||
abort ();
|
||
}
|
||
|
||
void
|
||
tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED)
|
||
{
|
||
}
|
||
|
||
#if defined OBJ_COFF
|
||
|
||
short
|
||
tc_coff_fix2rtype (fixS *fixP)
|
||
{
|
||
return (fixP->fx_r_type);
|
||
}
|
||
|
||
#endif /* OBJ_COFF */
|