231 lines
7.2 KiB
C
231 lines
7.2 KiB
C
/* collection of junk waiting time to sort out
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef M32R_SIM_H
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#define M32R_SIM_H
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/* gdb register numbers */
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#define PSW_REGNUM 16
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#define CBR_REGNUM 17
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#define SPI_REGNUM 18
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#define SPU_REGNUM 19
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#define BPC_REGNUM 20
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#define PC_REGNUM 21
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#define ACCL_REGNUM 22
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#define ACCH_REGNUM 23
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#define ACC1L_REGNUM 24
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#define ACC1H_REGNUM 25
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#define BBPSW_REGNUM 26
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#define BBPC_REGNUM 27
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extern int m32r_decode_gdb_ctrl_regnum (int);
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/* Cover macros for hardware accesses.
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FIXME: Eventually move to cgen. */
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#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
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extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
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extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
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extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
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extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
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extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
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extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
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extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
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extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
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extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
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extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
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extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
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extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
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extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
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extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
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extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
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extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
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extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
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extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
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/* Misc. profile data. */
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typedef struct {
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/* nop insn slot filler count */
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unsigned int fillnop_count;
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/* number of parallel insns */
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unsigned int parallel_count;
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/* FIXME: generalize this to handle all insn lengths, move to common. */
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/* number of short insns, not including parallel ones */
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unsigned int short_count;
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/* number of long insns */
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unsigned int long_count;
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/* Working area for computing cycle counts. */
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unsigned long insn_cycles; /* FIXME: delete */
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unsigned long cti_stall;
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unsigned long load_stall;
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unsigned long biggest_cycles;
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/* Bitmask of registers loaded by previous insn. */
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unsigned int load_regs;
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/* Bitmask of registers loaded by current insn. */
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unsigned int load_regs_pending;
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} M32R_MISC_PROFILE;
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/* Initialize the working area. */
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void m32r_init_insn_cycles (SIM_CPU *, int);
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/* Update the totals for the insn. */
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void m32r_record_insn_cycles (SIM_CPU *, int);
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/* This is invoked by the nop pattern in the .cpu file. */
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#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
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do { \
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if (PROFILE_INSN_P (cpu) \
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&& (addr & 3) != 0) \
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++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
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} while (0)
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/* This is invoked by the execute section of mloop{,x}.in. */
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#define PROFILE_COUNT_PARINSNS(cpu) \
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do { \
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if (PROFILE_INSN_P (cpu)) \
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++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
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} while (0)
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/* This is invoked by the execute section of mloop{,x}.in. */
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#define PROFILE_COUNT_SHORTINSNS(cpu) \
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do { \
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if (PROFILE_INSN_P (cpu)) \
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++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
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} while (0)
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/* This is invoked by the execute section of mloop{,x}.in. */
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#define PROFILE_COUNT_LONGINSNS(cpu) \
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do { \
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if (PROFILE_INSN_P (cpu)) \
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++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
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} while (0)
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#define GETTWI GETTSI
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#define SETTWI SETTSI
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/* Additional execution support. */
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/* Result of semantic function is one of
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- next address, branch only
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- NEW_PC_SKIP, sc/snc insn
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- NEW_PC_2, 2 byte non-branch non-sc/snc insn
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- NEW_PC_4, 4 byte non-branch insn
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The special values have bit 1 set so it's cheap to distinguish them.
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This works because all cti's are defined to zero the bottom two bits
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Note that the m32rx no longer doesn't implement its semantics with
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functions, so this isn't used. It's kept around should it be needed
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again. */
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/* FIXME: replace 0xffff0001 with 1? */
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#define NEW_PC_BASE 0xffff0001
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#define NEW_PC_SKIP NEW_PC_BASE
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#define NEW_PC_2 (NEW_PC_BASE + 2)
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#define NEW_PC_4 (NEW_PC_BASE + 4)
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#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
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/* Modify "next pc" support to handle parallel execution.
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This is for the non-pbb case. The m32rx no longer implements this.
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It's kept around should it be needed again. */
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#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
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#undef SEM_NEXT_VPC
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#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
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#undef SEM_SKIP_INSN
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#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
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#endif
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/* Hardware/device support.
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??? Will eventually want to move device stuff to config files. */
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/* Exception, Interrupt, and Trap addresses */
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#define EIT_SYSBREAK_ADDR 0x10
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#define EIT_RSVD_INSN_ADDR 0x20
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#define EIT_ADDR_EXCP_ADDR 0x30
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#define EIT_TRAP_BASE_ADDR 0x40
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#define EIT_EXTERN_ADDR 0x80
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#define EIT_RESET_ADDR 0x7ffffff0
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#define EIT_WAKEUP_ADDR 0x7ffffff0
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/* Special purpose traps. */
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#define TRAP_SYSCALL 0
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#define TRAP_BREAKPOINT 1
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/* Support for the MSPR register (Cache Purge Control Register)
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and the MCCR register (Cache Control Register) are needed in order for
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overlays to work correctly with the scache.
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MSPR no longer exists but is supported for upward compatibility with
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early overlay support. */
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/* Cache Purge Control (only exists on early versions of chips) */
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#define MSPR_ADDR 0xfffffff7
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#define MSPR_PURGE 1
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/* Lock Control Register (not supported) */
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#define MLCR_ADDR 0xfffffff7
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#define MLCR_LM 1
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/* Power Management Control Register (not supported) */
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#define MPMR_ADDR 0xfffffffb
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/* Cache Control Register */
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#define MCCR_ADDR 0xffffffff
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#define MCCR_CP 0x80
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/* not supported */
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#define MCCR_CM0 2
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#define MCCR_CM1 1
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/* Serial device addresses. */
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#ifdef M32R_EVA /* orig eva board, no longer supported */
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#define UART_INCHAR_ADDR 0xff102013
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#define UART_OUTCHAR_ADDR 0xff10200f
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#define UART_STATUS_ADDR 0xff102006
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/* Indicate ready bit is inverted. */
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#define UART_INPUT_READY0
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#else
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/* These are the values for the MSA2000 board.
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??? Will eventually need to move this to a config file. */
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#define UART_INCHAR_ADDR 0xff004009
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#define UART_OUTCHAR_ADDR 0xff004007
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#define UART_STATUS_ADDR 0xff004002
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#endif
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#define UART_INPUT_READY 0x4
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#define UART_OUTPUT_READY 0x1
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/* Start address and length of all device support. */
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#define M32R_DEVICE_ADDR 0xff000000
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#define M32R_DEVICE_LEN 0x01000000
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/* sim_core_attach device argument. */
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extern device m32r_devices;
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/* FIXME: Temporary, until device support ready. */
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struct _device { int foo; };
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/* Handle the trap insn. */
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USI m32r_trap (SIM_CPU *, PCADDR, int);
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#endif /* M32R_SIM_H */
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