d81352b8b8
(v850_callback): Declare.
(do_format_5): Fix extraction of OP[0].
(sim_size): Remove debugging printf.
(sim_set_callbacks): Do something useful.
(sim_stop_reason): Gross hacks to get c-torture running.
* simops.c: Simplify code for computing targets of bCC
insns. Invert 's' bit if 'ov' bit is set for some
instructions. Fix 'cy' bit handling for numerous
instructions. Make the simulator stop when a halt
instruction is encountered. Very crude support for
emulated syscalls (trap 0).
* v850_sim.h: Include "callback.h" and declare
v850_callback. Items in the operand array are 32bits.
Fixes & syscall stuff.
120 lines
4.2 KiB
Text
120 lines
4.2 KiB
Text
Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c: OP should be an array of 32bit operands!
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(v850_callback): Declare.
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(do_format_5): Fix extraction of OP[0].
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(sim_size): Remove debugging printf.
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(sim_set_callbacks): Do something useful.
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(sim_stop_reason): Gross hacks to get c-torture running.
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* simops.c: Simplify code for computing targets of bCC
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insns. Invert 's' bit if 'ov' bit is set for some
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instructions. Fix 'cy' bit handling for numerous
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instructions. Make the simulator stop when a halt
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instruction is encountered. Very crude support for
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emulated syscalls (trap 0).
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* v850_sim.h: Include "callback.h" and declare
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v850_callback. Items in the operand array are 32bits.
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Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (sim_resume): Fix code to check for a format 3
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opcode.
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* simops.c: bCC insns only argument is a constant, not a
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register value (duh...)
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Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix "not1" and "set1".
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* simops.c: Don't forget to initialize temp for
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"ld.h" and "ld.w"
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* interp.c: Remove various debugging printfs.
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* simops.c: Fix satadd, satsub boundary case handling.
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* interp.c (hash): Fix.
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* interp.c (do_format_8): Get operands correctly and
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call the target function.
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* simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
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Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (do_format_4): Get operands correctly and
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call the target function.
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* simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
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"sst.h", and "sst.w".
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* v850_sim.h: The V850 doesn't have split I&D spaces. Change
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accordingly. Remove many unused definitions.
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* interp.c: The V850 doesn't have split I&D spaces. Change
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accordingly.
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(get_longlong, get_longword, get_word): Deleted.
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(write_longlong, write_longword, write_word): Deleted.
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(get_operands): Deleted.
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(get_byte, get_half, get_word): New functions.
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(put_byte, put_half, put_word): New functions.
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* simops.c: Remove unused functions. Rough cut at
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"ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
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* v850_sim.h (struct _state): Remove "psw" field. Add
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"sregs" field.
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(PSW): Remove bogus definition.
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* simops.c: Change condition code handling to use the psw
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register within the sregs array. Handle "ldsr" and "stsr".
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* simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
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* interp.c (do_format_5): Get operands correctly and
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call the target function.
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(sim_resume): Don't do a PC update for format 5 instructions.
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* simops.c: Handle "jarl" and "jmp" instructions.
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* simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
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"di", and "ei" instructions correctly.
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* interp.c (do_format_3): Get operands correctly and call
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the target function.
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* simops.c: Handle bCC instructions.
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* simops.c: Add condition code handling to shift insns.
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Fix minor typos in condition code handling for other insns.
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* Makefile.in: Fix typo.
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* simops.c: Add condition code handling to "sub" "subr" and
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"divh" instructions.
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* interp.c (hash): Update to be more accurate.
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(lookup_hash): Call hash rather than computing the hash
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code here.
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(do_format_1_2): Handle format 1 and format 2 instructions.
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Get operands correctly and call the target function.
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(do_format_6): Get operands correctly and call the target
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function.
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(do_formats_9_10): Rough cut so shift ops will work.
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(sim_resume): Tweak to deal with format 1 and format 2
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handling in a single funtion. Don't update the PC
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for format 3 insns. Fix typos.
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* simops.c: Slightly reorganize. Add condition code handling
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to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
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and "not" instructions.
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* v850_sim.h (reg_t): Registers are 32bits.
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(_state): The V850 has 32 general registers. Add a 32bit
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psw and pc register too. Add accessor macros
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* Makefile.in, interp.c, v850_sim.h: Bring over endianness
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changes from the d10v simulator.
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* simops.c: Add shift support.
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* simops.c: Add multiply & divide support. Abort for system
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instructions.
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* simops.c: Add logicals, mov, movhi, movea, add, addi, sub
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and subr. No condition codes yet.
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Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
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* ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
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gencode.c, interp.c, simops.c: Created.
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