585 lines
22 KiB
C
585 lines
22 KiB
C
/* Definitions to make GDB run on a mips box under 4.3bsd.
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Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
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Free Software Foundation, Inc.
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Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
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and by Alessandro Forin (af@cs.cmu.edu) at CMU..
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#ifndef TM_MIPS_H
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#define TM_MIPS_H 1
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struct frame_info;
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struct symbol;
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struct type;
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struct value;
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#include <bfd.h>
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#include "coff/sym.h" /* Needed for PDR below. */
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#include "coff/symconst.h"
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#if !defined (TARGET_BYTE_ORDER_DEFAULT)
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#define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
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#endif
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#if !defined (GDB_TARGET_IS_MIPS64)
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#define GDB_TARGET_IS_MIPS64 0
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#endif
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#if !defined (MIPS_EABI)
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#define MIPS_EABI 0
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#endif
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#if !defined (TARGET_MONITOR_PROMPT)
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#define TARGET_MONITOR_PROMPT "<IDT>"
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#endif
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/* PC should be masked to remove possible MIPS16 flag */
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#if !defined (GDB_TARGET_MASK_DISAS_PC)
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#define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
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#endif
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#if !defined (GDB_TARGET_UNMASK_DISAS_PC)
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#define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
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#endif
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/* Floating point is IEEE compliant */
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#define IEEE_FLOAT
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/* The name of the usual type of MIPS processor that is in the target
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system. */
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#define DEFAULT_MIPS_TYPE "generic"
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/* Remove useless bits from an instruction address. */
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#define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
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CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
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/* Remove useless bits from the stack pointer. */
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#define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
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/* Offset from address of function to start of its code.
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Zero on most machines. */
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#define FUNCTION_START_OFFSET 0
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/* Advance PC across any function entry prologue instructions
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to reach some "real" code. */
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#define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
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extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
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/* Return non-zero if PC points to an instruction which will cause a step
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to execute both the instruction at PC and an instruction at PC+4. */
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extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
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#define STEP_SKIPS_DELAY_P (1)
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#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
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/* Immediately after a function call, return the saved pc.
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Can't always go through the frames for this because on some machines
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the new frame is not set up until the new function executes
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some instructions. */
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#define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
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/* Are we currently handling a signal */
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extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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#define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
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/* Stack grows downward. */
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#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
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/* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
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16- or 32-bit breakpoint should be used. It returns a pointer
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to a string of bytes that encode a breakpoint instruction, stores
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the length of the string to *lenptr, and adjusts the pc (if necessary) to
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point to the actual memory location where the breakpoint should be
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inserted. */
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extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
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#define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
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/* Amount PC must be decremented by after a breakpoint.
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This is often the number of bytes in BREAKPOINT
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but not always. */
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#define DECR_PC_AFTER_BREAK 0
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/* Say how long (ordinary) registers are. This is a piece of bogosity
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used in push_word and a few other places; REGISTER_RAW_SIZE is the
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real way to know how big a register is. */
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#define REGISTER_SIZE 4
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/* The size of a register. This is predefined in tm-mips64.h. We
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can't use REGISTER_SIZE because that is used for various other
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things. */
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#ifndef MIPS_REGSIZE
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#define MIPS_REGSIZE 4
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#endif
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/* The sizes of floating point registers. */
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#define MIPS_FPU_SINGLE_REGSIZE 4
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#define MIPS_FPU_DOUBLE_REGSIZE 8
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/* Number of machine registers */
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#ifndef NUM_REGS
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#define NUM_REGS 90
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#endif
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/* Given the register index, return the name of the corresponding
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register. */
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extern char *mips_register_name PARAMS ((int regnr));
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#define REGISTER_NAME(i) mips_register_name (i)
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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#ifndef MIPS_REGISTER_NAMES
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#define MIPS_REGISTER_NAMES \
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{ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
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"sr", "lo", "hi", "bad", "cause","pc", \
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
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"fsr", "fir", "fp", "", \
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"", "", "", "", "", "", "", "", \
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"", "", "", "", "", "", "", "", \
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}
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#endif
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/* Register numbers of various important registers.
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Note that some of these values are "real" register numbers,
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and correspond to the general registers of the machine,
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and some are "phony" register numbers which are too large
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to be actual register numbers as far as the user is concerned
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but do serve to get the desired values when passed to read_register. */
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#define ZERO_REGNUM 0 /* read-only register, always 0 */
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#define V0_REGNUM 2 /* Function integer return value */
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#define A0_REGNUM 4 /* Loc of first arg during a subr call */
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#if MIPS_EABI
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#define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
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#define MIPS_NUM_ARG_REGS 8
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#else
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#define MIPS_LAST_ARG_REGNUM 7 /* old ABI uses R4 through R7 for args */
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#define MIPS_NUM_ARG_REGS 4
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#endif
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#define T9_REGNUM 25 /* Contains address of callee in PIC */
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#define SP_REGNUM 29 /* Contains address of top of stack */
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#define RA_REGNUM 31 /* Contains return address value */
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#define PS_REGNUM 32 /* Contains processor status */
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#define HI_REGNUM 34 /* Multiple/divide temp */
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#define LO_REGNUM 33 /* ... */
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#define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
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#define CAUSE_REGNUM 36 /* describes last exception */
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#define PC_REGNUM 37 /* Contains program counter */
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#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
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#define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */
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#if MIPS_EABI /* EABI uses F12 through F19 for args */
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#define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
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#define MIPS_NUM_FP_ARG_REGS 8
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#else /* old ABI uses F12 through F15 for args */
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#define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
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#define MIPS_NUM_FP_ARG_REGS 4
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#endif
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#define FCRCS_REGNUM 70 /* FP control/status */
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#define FCRIR_REGNUM 71 /* FP implementation/revision */
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#define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
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#define UNUSED_REGNUM 73 /* Never used, FIXME */
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#define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */
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#define PRID_REGNUM 89 /* Processor ID */
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#define LAST_EMBED_REGNUM 89 /* Last one */
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/* Define DO_REGISTERS_INFO() to do machine-specific formatting
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of register dumps. */
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#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
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extern void mips_do_registers_info PARAMS ((int, int));
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
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/* Index within `registers' of the first byte of the space for
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register N. */
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#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
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/* Number of bytes of storage in the actual machine representation for
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register N. NOTE: This indirectly defines the register size
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transfered by the GDB protocol. */
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extern int mips_register_raw_size PARAMS ((int reg_nr));
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#define REGISTER_RAW_SIZE(N) (mips_register_raw_size ((N)))
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/* Covert between the RAW and VIRTUAL registers.
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Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
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really 32 bit registers. This is a legacy of the 64 bit MIPS GDB
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protocol which transfers 64 bits for 32 bit registers. */
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extern int mips_register_convertible PARAMS ((int reg_nr));
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#define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
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void mips_register_convert_to_virtual PARAMS ((int reg_nr, struct type *virtual_type, char *raw_buf, char *virt_buf));
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#define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
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mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
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void mips_register_convert_to_raw PARAMS ((struct type *virtual_type, int reg_nr, char *virt_buf, char *raw_buf));
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#define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
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mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
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/* Number of bytes of storage in the program's representation
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for register N. */
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#define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
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/* Largest value REGISTER_RAW_SIZE can have. */
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#define MAX_REGISTER_RAW_SIZE 8
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/* Largest value REGISTER_VIRTUAL_SIZE can have. */
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#define MAX_REGISTER_VIRTUAL_SIZE 8
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/* Return the GDB type object for the "standard" data type of data in
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register N. */
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#ifndef REGISTER_VIRTUAL_TYPE
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#define REGISTER_VIRTUAL_TYPE(N) \
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(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
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: ((N) == 32 /*SR*/) ? builtin_type_uint32 \
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: ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
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: builtin_type_int)
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#endif
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/* All mips targets store doubles in a register pair with the least
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significant register in the lower numbered register.
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If the target is big endian, double register values need conversion
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between memory and register formats. */
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#define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
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do {if (TARGET_BYTE_ORDER == BIG_ENDIAN \
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&& REGISTER_RAW_SIZE (n) == 4 \
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&& (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 \
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&& TYPE_CODE(type) == TYPE_CODE_FLT \
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&& TYPE_LENGTH(type) == 8) { \
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char __temp[4]; \
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memcpy (__temp, ((char *)(buffer))+4, 4); \
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memcpy (((char *)(buffer))+4, (buffer), 4); \
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memcpy (((char *)(buffer)), __temp, 4); }} while (0)
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#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
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do {if (TARGET_BYTE_ORDER == BIG_ENDIAN \
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&& REGISTER_RAW_SIZE (n) == 4 \
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&& (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 \
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&& TYPE_CODE(type) == TYPE_CODE_FLT \
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&& TYPE_LENGTH(type) == 8) { \
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char __temp[4]; \
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memcpy (__temp, ((char *)(buffer))+4, 4); \
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memcpy (((char *)(buffer))+4, (buffer), 4); \
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memcpy (((char *)(buffer)), __temp, 4); }} while (0)
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/* Store the address of the place in which to copy the structure the
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subroutine will return. Handled by mips_push_arguments. */
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#define STORE_STRUCT_RETURN(addr, sp)
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/**/
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/* Extract from an array REGBUF containing the (raw) register state
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a function return value of type TYPE, and copy that, in virtual format,
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into VALBUF. XXX floats */
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#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
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mips_extract_return_value(TYPE, REGBUF, VALBUF)
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extern void
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mips_extract_return_value PARAMS ((struct type *, char[], char *));
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/* Write into appropriate registers a function return value
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of type TYPE, given in virtual format. */
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#define STORE_RETURN_VALUE(TYPE,VALBUF) \
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mips_store_return_value(TYPE, VALBUF)
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extern void mips_store_return_value PARAMS ((struct type *, char *));
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/* Extract from an array REGBUF containing the (raw) register state
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the address in which a function should return its structure value,
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as a CORE_ADDR (or an expression that can be used as one). */
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/* The address is passed in a0 upon entry to the function, but when
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the function exits, the compiler has copied the value to v0. This
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convention is specified by the System V ABI, so I think we can rely
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on it. */
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
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(extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
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REGISTER_RAW_SIZE (V0_REGNUM)))
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extern use_struct_convention_fn mips_use_struct_convention;
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#define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
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/* Describe the pointer in each stack frame to the previous stack frame
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(its caller). */
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/* FRAME_CHAIN takes a frame's nominal address
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and produces the frame's chain-pointer. */
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#define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
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extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
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/* Define other aspects of the stack frame. */
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/* A macro that tells us whether the function invocation represented
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by FI does not have a frame on the stack associated with it. If it
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does not, FRAMELESS is set to 1, else 0. */
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/* We handle this differently for mips, and maybe we should not */
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#define FRAMELESS_FUNCTION_INVOCATION(FI) (0)
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/* Saved Pc. */
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#define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME))
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extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
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#define FRAME_ARGS_ADDRESS(fi) (fi)->frame
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#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
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/* Return number of args passed to a frame.
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Can return -1, meaning no way to tell. */
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#define FRAME_NUM_ARGS(fi) (mips_frame_num_args(fi))
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extern int mips_frame_num_args PARAMS ((struct frame_info *));
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/* Return number of bytes at start of arglist that are not really args. */
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#define FRAME_ARGS_SKIP 0
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/* Put here the code to store, into a struct frame_saved_regs,
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the addresses of the saved registers of frame described by FRAME_INFO.
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This includes special registers such as pc and fp saved in special
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ways in the stack frame. sp is even more special:
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the address we return for it IS the sp for the next frame. */
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#define FRAME_INIT_SAVED_REGS(frame_info) \
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do { \
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if ((frame_info)->saved_regs == NULL) \
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mips_find_saved_regs (frame_info); \
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(frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
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} while (0)
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extern void mips_find_saved_regs PARAMS ((struct frame_info *));
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/* Things needed for making the inferior call functions. */
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/* Stack must be aligned on 32-bit boundaries when synthesizing
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function calls. We don't need STACK_ALIGN, PUSH_ARGUMENTS will
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handle it. */
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extern CORE_ADDR mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
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#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
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(mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
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extern CORE_ADDR mips_push_return_address PARAMS ((CORE_ADDR pc, CORE_ADDR sp));
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#define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
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/* Push an empty stack frame, to record the current PC, etc. */
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#define PUSH_DUMMY_FRAME mips_push_dummy_frame()
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extern void mips_push_dummy_frame PARAMS ((void));
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/* Discard from the stack the innermost frame, restoring all registers. */
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#define POP_FRAME mips_pop_frame()
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extern void mips_pop_frame PARAMS ((void));
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#define CALL_DUMMY { 0 }
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#define CALL_DUMMY_START_OFFSET (0)
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#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
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/* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
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It doesn't hurt to do this on other systems; $t9 will be ignored. */
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#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
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write_register(T9_REGNUM, fun)
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#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
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#define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
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extern CORE_ADDR mips_call_dummy_address PARAMS ((void));
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/* There's a mess in stack frame creation. See comments in blockframe.c
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near reference to INIT_FRAME_PC_FIRST. */
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|
||
#define INIT_FRAME_PC(fromleaf, prev) /* nada */
|
||
|
||
#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
|
||
mips_init_frame_pc_first(fromleaf, prev)
|
||
extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
|
||
|
||
/* Special symbol found in blocks associated with routines. We can hang
|
||
mips_extra_func_info_t's off of this. */
|
||
|
||
#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
|
||
extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
|
||
|
||
/* Specific information about a procedure.
|
||
This overlays the MIPS's PDR records,
|
||
mipsread.c (ab)uses this to save memory */
|
||
|
||
typedef struct mips_extra_func_info
|
||
{
|
||
long numargs; /* number of args to procedure (was iopt) */
|
||
bfd_vma high_addr; /* upper address bound */
|
||
long frame_adjust; /* offset of FP from SP (used on MIPS16) */
|
||
PDR pdr; /* Procedure descriptor record */
|
||
}
|
||
*mips_extra_func_info_t;
|
||
|
||
extern void mips_init_extra_frame_info PARAMS ((int fromleaf, struct frame_info *));
|
||
#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
|
||
mips_init_extra_frame_info(fromleaf, fci)
|
||
|
||
extern void mips_print_extra_frame_info PARAMS ((struct frame_info * frame));
|
||
#define PRINT_EXTRA_FRAME_INFO(fi) \
|
||
mips_print_extra_frame_info (fi)
|
||
|
||
/* It takes two values to specify a frame on the MIPS.
|
||
|
||
In fact, the *PC* is the primary value that sets up a frame. The
|
||
PC is looked up to see what function it's in; symbol information
|
||
from that function tells us which register is the frame pointer
|
||
base, and what offset from there is the "virtual frame pointer".
|
||
(This is usually an offset from SP.) On most non-MIPS machines,
|
||
the primary value is the SP, and the PC, if needed, disambiguates
|
||
multiple functions with the same SP. But on the MIPS we can't do
|
||
that since the PC is not stored in the same part of the frame every
|
||
time. This does not seem to be a very clever way to set up frames,
|
||
but there is nothing we can do about that). */
|
||
|
||
#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
|
||
extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
|
||
|
||
/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
|
||
|
||
#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
|
||
|
||
/* Convert a ecoff register number to a gdb REGNUM */
|
||
|
||
#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
|
||
|
||
/* If the current gcc for for this target does not produce correct debugging
|
||
information for float parameters, both prototyped and unprototyped, then
|
||
define this macro. This forces gdb to always assume that floats are
|
||
passed as doubles and then converted in the callee.
|
||
|
||
For the mips chip, it appears that the debug info marks the parameters as
|
||
floats regardless of whether the function is prototyped, but the actual
|
||
values are passed as doubles for the non-prototyped case and floats for
|
||
the prototyped case. Thus we choose to make the non-prototyped case work
|
||
for C and break the prototyped case, since the non-prototyped case is
|
||
probably much more common. (FIXME). */
|
||
|
||
#define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
|
||
|
||
/* Select the default mips disassembler */
|
||
|
||
#define TM_PRINT_INSN_MACH 0
|
||
|
||
|
||
/* These are defined in mdebugread.c and are used in mips-tdep.c */
|
||
extern CORE_ADDR sigtramp_address, sigtramp_end;
|
||
extern void fixup_sigtramp PARAMS ((void));
|
||
|
||
/* Defined in mips-tdep.c and used in remote-mips.c */
|
||
extern char *mips_read_processor_type PARAMS ((void));
|
||
|
||
/* Functions for dealing with MIPS16 call and return stubs. */
|
||
#define IN_SOLIB_CALL_TRAMPOLINE(pc, name) mips_in_call_stub (pc, name)
|
||
#define IN_SOLIB_RETURN_TRAMPOLINE(pc, name) mips_in_return_stub (pc, name)
|
||
#define SKIP_TRAMPOLINE_CODE(pc) mips_skip_stub (pc)
|
||
#define IGNORE_HELPER_CALL(pc) mips_ignore_helper (pc)
|
||
extern int mips_in_call_stub PARAMS ((CORE_ADDR pc, char *name));
|
||
extern int mips_in_return_stub PARAMS ((CORE_ADDR pc, char *name));
|
||
extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
|
||
extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
|
||
|
||
#ifndef TARGET_MIPS
|
||
#define TARGET_MIPS
|
||
#endif
|
||
|
||
/* Definitions and declarations used by mips-tdep.c and remote-mips.c */
|
||
#define MIPS_INSTLEN 4 /* Length of an instruction */
|
||
#define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16 */
|
||
#define MIPS_NUMREGS 32 /* Number of integer or float registers */
|
||
typedef unsigned long t_inst; /* Integer big enough to hold an instruction */
|
||
|
||
/* MIPS16 function addresses are odd (bit 0 is set). Here are some
|
||
macros to test, set, or clear bit 0 of addresses. */
|
||
#define IS_MIPS16_ADDR(addr) ((addr) & 1)
|
||
#define MAKE_MIPS16_ADDR(addr) ((addr) | 1)
|
||
#define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
|
||
|
||
#endif /* TM_MIPS_H */
|
||
|
||
/* Macros for setting and testing a bit in a minimal symbol that
|
||
marks it as 16-bit function. The MSB of the minimal symbol's
|
||
"info" field is used for this purpose. This field is already
|
||
being used to store the symbol size, so the assumption is
|
||
that the symbol size cannot exceed 2^31.
|
||
|
||
ELF_MAKE_MSYMBOL_SPECIAL
|
||
tests whether an ELF symbol is "special", i.e. refers
|
||
to a 16-bit function, and sets a "special" bit in a
|
||
minimal symbol to mark it as a 16-bit function
|
||
MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
|
||
MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
|
||
the "info" field with the "special" bit masked out
|
||
*/
|
||
|
||
#define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
|
||
{ \
|
||
if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
|
||
MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
|
||
SYMBOL_VALUE_ADDRESS (msym) |= 1; \
|
||
} \
|
||
}
|
||
|
||
#define MSYMBOL_IS_SPECIAL(msym) \
|
||
(((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
|
||
#define MSYMBOL_SIZE(msym) \
|
||
((long) MSYMBOL_INFO (msym) & 0x7fffffff)
|
||
|
||
|
||
/* Command to set the processor type. */
|
||
extern void mips_set_processor_type_command (char *, int);
|