8fdcc58daa
* spu.h (R_SPU_ADD_PIC): New.
bfd/
* reloc.c (BFD_RELOC_SPU_ADD_PIC): Define.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-spu.c (elf_howto_table): Add entries SPU_ADD_PIC.
(spu_elf_bfd_to_reloc_type): Handle SPU_ADD_PIC.
(spu_elf_relocate_section): Patch instructions marked by SPU_ADD_PIC.
gas/
* config/tc-spu.c (md_apply_fix): Handle SPU_ADD_PIC.
* config/tc-spu.h (tc_fix_adjustable): Don't adjust for SPU_ADD_PIC.
(TC_FORCE_RELOCATION): Emit relocs for SPU_ADD_PIC.
ld/testsuite/
* ld-spu/pic.d: New.
* ld-spu/pic.s: New.
* ld-spu/picdef.s: New.
105 lines
2.4 KiB
Makefile
105 lines
2.4 KiB
Makefile
#source: pic.s
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#source: picdef.s
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#ld: --emit-relocs
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#objdump: -D -r
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.*elf32-spu
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Disassembly of section \.text:
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00000000 <before>:
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\.\.\.
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00000008 <_start>:
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8: 42 00 08 02 ila \$2,10 <_start\+0x8>
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8: SPU_ADDR18 \.text\+0x10
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c: 33 00 00 fe brsl \$126,10 <_start\+0x8>
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c: SPU_REL16 \.text\+0x10
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10: 08 1f 81 7e sf \$126,\$2,\$126
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14: 42 00 02 04 ila \$4,4 <before\+0x4>
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14: SPU_ADDR18 \.text\+0x4
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18: 42 00 42 05 ila \$5,84 <end>
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18: SPU_ADDR18 \.text\+0x84
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1c: 42 00 04 06 ila \$6,8 <_start>
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1c: SPU_ADDR18 _start
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20: 42 00 42 07 ila \$7,84 <end>
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20: SPU_ADDR18 \.text\+0x84
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24: 18 1f 82 04 a \$4,\$4,\$126
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24: SPU_ADD_PIC before\+0x4
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28: 18 1f 82 85 a \$5,\$5,\$126
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28: SPU_ADD_PIC after\+0xfffffffc
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2c: 18 1f 83 06 a \$6,\$6,\$126
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2c: SPU_ADD_PIC _start
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30: 18 1f 83 87 a \$7,\$7,\$126
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30: SPU_ADD_PIC end
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34: 42 00 00 0e ila \$14,0
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34: SPU_ADDR18 \.text
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38: 18 1f 87 0e a \$14,\$14,\$126
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38: SPU_ADD_PIC before
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3c: 42 00 00 03 ila \$3,0
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3c: SPU_ADDR18 undef
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40: 1c 00 01 83 ai \$3,\$3,0
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40: SPU_ADD_PIC undef
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44: 41 00 00 07 ilhu \$7,0
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44: SPU_ADDR16_HI ext
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48: 60 ab 3c 07 iohl \$7,22136 # 5678
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48: SPU_ADDR16_LO ext
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4c: 18 1f 83 84 a \$4,\$7,\$126
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4c: SPU_ADD_PIC ext
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50: 42 00 80 09 ila \$9,100 <loc>
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50: SPU_ADDR18 \.data
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54: 18 1f 84 85 a \$5,\$9,\$126
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54: SPU_ADD_PIC loc
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58: 42 00 88 08 ila \$8,110 <glob>
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58: SPU_ADDR18 glob
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5c: 18 1f 84 06 a \$6,\$8,\$126
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5c: SPU_ADD_PIC glob
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60: 42 00 90 09 ila \$9,120 <__bss_start>
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60: SPU_ADDR18 _end
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64: 18 1f 84 89 a \$9,\$9,\$126
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64: SPU_ADD_PIC _end
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68: 12 02 39 85 hbrr 7c <acall>,1234 <abscall> # 1234
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68: SPU_REL16 abscall
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6c: 33 ff f2 82 lqr \$2,0 <before>
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6c: SPU_REL16 undef
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70: 23 ff f2 02 stqr \$2,0 <before>
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70: SPU_REL16 undef
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74: 33 8a c0 83 lqr \$3,5678 <ext> # 5678
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74: SPU_REL16 ext
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78: 33 8a c2 04 lqr \$4,5688 <ext\+0x10> # 5688
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78: SPU_REL16 ext\+0x10
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0000007c <acall>:
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7c: 33 02 37 00 brsl \$0,1234 <abscall> # 1234
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7c: SPU_REL16 abscall
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80: 32 02 36 80 br 1234 <abscall> # 1234
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80: SPU_REL16 abscall
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00000084 <end>:
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84: 00 00 00 00 stop
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00000088 <after>:
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88: 00 00 00 00 stop
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Disassembly of section \.data:
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00000100 <loc>:
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100: 00 00 00 01 stop
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\.\.\.
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00000110 <glob>:
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110: 00 00 00 02 stop
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\.\.\.
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Disassembly of section \.note\.spu_name:
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00000000 <\.note\.spu_name>:
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.*
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.*
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.*
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.*
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.*
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.*
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.*
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#pass
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