2e8cf49e13
sim * configure.tgt: Add aarch64 entry. * configure: Regenerate. * sim/aarch64/configure.ac: New configure template. * sim/aarch64/aclocal.m4: Generate. * sim/aarch64/config.in: Generate. * sim/aarch64/configure: Generate. * sim/aarch64/cpustate.c: New file - functions for accessing AArch64 registers. * sim/aarch64/cpustate.h: New header. * sim/aarch64/decode.h: New header. * sim/aarch64/interp.c: New file - interface between GDB and simulator. * sim/aarch64/Makefile.in: New makefile template. * sim/aarch64/memory.c: New file - functions for simulating aarch64 memory accesses. * sim/aarch64/memory.h: New header. * sim/aarch64/sim-main.h: New header. * sim/aarch64/simulator.c: New file - aarch64 simulator functions. * sim/aarch64/simulator.h: New header. include/gdb * sim-aarch64.h: New file. sim/test * configure: Regenerate. * sim/aarch64: New directory.
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/* sim-main.h -- Interface with sim/common.
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Copyright (C) 2015 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef _SIM_MAIN_H
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#define _SIM_MAIN_H
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#include "sim-basics.h"
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#include "sim-types.h"
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#include "sim-base.h"
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#include "sim-base.h"
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#include "sim-io.h"
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#include "cpustate.h"
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/* A per-core state structure. */
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struct _sim_cpu
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{
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GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
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FRegister fr[32];
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uint64_t pc;
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uint32_t CPSR;
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uint32_t FPSR;
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uint64_t nextpc;
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uint32_t instr;
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sim_cpu_base base;
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};
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typedef enum
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{
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AARCH64_MIN_GR = 0,
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AARCH64_MAX_GR = 31,
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AARCH64_MIN_FR = 32,
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AARCH64_MAX_FR = 63,
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AARCH64_PC_REGNO = 64,
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AARCH64_CPSR_REGNO = 65,
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AARCH64_FPSR_REGNO = 66,
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AARCH64_MAX_REGNO = 67
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} aarch64_regno;
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/* The simulator state structure used to hold all global variables. */
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struct sim_state
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{
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sim_cpu * cpu[MAX_NR_PROCESSORS];
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sim_state_base base;
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};
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#endif /* _SIM_MAIN_H */
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