488 lines
14 KiB
C
488 lines
14 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _CONFIG_H_
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#define _CONFIG_H_
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/* endianness of the host/target:
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If the build process is aware (at compile time) of the endianness
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of the host/target it is able to eliminate slower generic endian
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handling code.
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Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */
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#ifndef WITH_HOST_BYTE_ORDER
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#define WITH_HOST_BYTE_ORDER 0 /*unknown*/
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#endif
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#ifndef WITH_TARGET_BYTE_ORDER
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#define WITH_TARGET_BYTE_ORDER 0 /*unknown*/
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#endif
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extern int current_host_byte_order;
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#define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \
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? WITH_HOST_BYTE_ORDER \
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: current_host_byte_order)
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extern int current_target_byte_order;
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#define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \
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? WITH_TARGET_BYTE_ORDER \
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: current_target_byte_order)
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/* Intel host BSWAP support:
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Whether to use bswap on the 486 and pentiums rather than the 386
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sequence that uses xchgb/rorl/xchgb */
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#ifndef WITH_BSWAP
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#define WITH_BSWAP 0
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#endif
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/* SMP support:
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Sets a limit on the number of processors that can be simulated. If
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WITH_SMP is set to zero (0), the simulator is restricted to
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suporting only on processor (and as a consequence leaves the SMP
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code out of the build process).
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The actual number of processors is taken from the device
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/options/smp@<nr-cpu> */
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#ifndef WITH_SMP
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#define WITH_SMP 2
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#endif
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#if WITH_SMP
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#define MAX_NR_PROCESSORS WITH_SMP
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#else
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#define MAX_NR_PROCESSORS 1
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#endif
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/* Word size of host/target:
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Set these according to your host and target requirements. At this
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point in time, I've only compiled (not run) for a 64bit and never
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built for a 64bit host. This will always remain a compile time
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option */
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#ifndef WITH_TARGET_WORD_BITSIZE
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#define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */
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#endif
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#ifndef WITH_HOST_WORD_BITSIZE
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#define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */
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#endif
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/* Program environment:
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Three environments are available - UEA (user), VEA (virtual) and
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OEA (perating). The former two are environment that users would
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expect to see (VEA includes things like coherency and the time
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base) while OEA is what an operating system expects to see. By
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setting these to specific values, the build process is able to
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eliminate non relevent environment code
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CURRENT_ENVIRONMENT specifies which of vea or oea is required for
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the current runtime. */
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#define USER_ENVIRONMENT 1
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#define VIRTUAL_ENVIRONMENT 2
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#define OPERATING_ENVIRONMENT 3
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#ifndef WITH_ENVIRONMENT
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#define WITH_ENVIRONMENT 0
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#endif
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extern int current_environment;
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#define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
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? WITH_ENVIRONMENT \
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: current_environment)
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/* Optional VEA/OEA code:
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The below, required for the OEA model may also be included in the
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VEA model however, as far as I can tell only make things
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slower... */
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/* Events. Devices modeling real H/W need to be able to efficiently
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schedule things to do at known times in the future. The event
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queue implements this. Unfortunatly this adds the need to check
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for any events once each full instruction cycle. */
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#define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT)
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/* Time base:
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The PowerPC architecture includes the addition of both a time base
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register and a decrement timer. Like events adds to the overhead
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of of some instruction cycles. */
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#ifndef WITH_TIME_BASE
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#define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT)
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#endif
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/* Callback/Default Memory.
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Core includes a builtin memory type (raw_memory) that is
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implemented using an array. raw_memory does not require any
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additional functions etc.
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Callback memory is where the core calls a core device for the data
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it requires.
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Default memory is an extenstion of this where for addresses that do
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not map into either a callback or core memory range a default map
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can be used.
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The OEA model uses callback memory for devices and default memory
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for buses.
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The VEA model uses callback memory to capture `page faults'.
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While it may be possible to eliminate callback/default memory (and
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hence also eliminate an additional test per memory fetch) it
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probably is not worth the effort.
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BTW, while raw_memory could have been implemented as a callback,
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profiling has shown that there is a biger win (at least for the
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x86) in eliminating a function call for the most common
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(raw_memory) case. */
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#define WITH_CALLBACK_MEMORY 1
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/* Alignment:
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The PowerPC may or may not handle miss aligned transfers. An
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implementation normally handles miss aligned transfers in big
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endian mode but generates an exception in little endian mode.
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This model. Instead allows both little and big endian modes to
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either take exceptions or handle miss aligned transfers.
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If 0 is specified then for big-endian mode miss alligned accesses
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are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
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processor will fault on them (STRICT_ALIGNMENT). */
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#define NONSTRICT_ALIGNMENT 1
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#define STRICT_ALIGNMENT 2
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#ifndef WITH_ALIGNMENT
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#define WITH_ALIGNMENT 0
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#endif
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extern int current_alignment;
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#define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
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? WITH_ALIGNMENT \
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: current_alignment)
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/* Floating point suport:
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Still under development. */
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#define SOFT_FLOATING_POINT 1
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#define HARD_FLOATING_POINT 2
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#ifndef WITH_FLOATING_POINT
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#define WITH_FLOATING_POINT HARD_FLOATING_POINT
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#endif
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extern int current_floating_point;
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#define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
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? WITH_FLOATING_POINT \
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: current_floating_point)
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/* Debugging:
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Control the inclusion of debugging code. */
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/* Include the tracing code. Disabling this eliminates all tracing
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code */
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#ifndef WITH_TRACE
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#define WITH_TRACE 1
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#endif
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/* include code that checks assertions scattered through out the
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program */
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#ifndef WITH_ASSERT
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#define WITH_ASSERT 1
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#endif
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/* Whether to check instructions for reserved bits being set */
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#ifndef WITH_RESERVED_BITS
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#define WITH_RESERVED_BITS 1
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#endif
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/* include monitoring code */
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#define MONITOR_INSTRUCTION_ISSUE 1
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#define MONITOR_LOAD_STORE_UNIT 2
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#ifndef WITH_MON
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#define WITH_MON (MONITOR_LOAD_STORE_UNIT \
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| MONITOR_INSTRUCTION_ISSUE)
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#endif
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/* Include code that simulates function units to model particular
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machines more closely and provide more detailed information about
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optimization potential. */
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#ifndef WITH_FUNCTION_UNIT
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#define WITH_FUNCTION_UNIT 1
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#endif
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/* Which specific processor to model */
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typedef enum _ppc_model {
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PPC_MODEL_UNKNOWN,
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PPC_MODEL_601,
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PPC_MODEL_602,
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PPC_MODEL_603,
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PPC_MODEL_603e,
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PPC_MODEL_604,
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PPC_MODEL_403,
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PPC_MODEL_505,
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PPC_MODEL_821,
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PPC_MODEL_860
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} ppc_model;
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#ifndef WITH_DEFAULT_PPC_MODEL
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#define WITH_DEFAULT_PPC_MODEL PPC_MODEL_603e
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#endif
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extern ppc_model current_ppc_model;
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#ifndef WITH_PPC_MODEL
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#define WITH_PPC_MODEL 0
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#endif
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#define CURRENT_PPC_MODEL (WITH_PPC_MODEL \
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? WITH_PPC_MODEL \
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: current_ppc_model)
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/* Current CPU model (models are in the generated models.h include file) */
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#ifndef WITH_MODEL
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#define WITH_MODEL 0
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#endif
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#define CURRENT_MODEL (WITH_MODEL \
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? WITH_MODEL \
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: current_model)
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#ifndef WITH_DEFAULT_MODEL
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#define WITH_DEFAULT_MODEL DEFAULT_MODEL
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#endif
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/* INLINE CODE SELECTION:
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GCC -O3 attempts to inline any function or procedure in scope. The
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options below facilitate fine grained control over what is and what
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isn't made inline. For instance it can control things down to a
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specific modules static routines. This control is implemented in
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two parts. Doing this allows the compiler to both eliminate the
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overhead of function calls and (as a consequence) also eliminate
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further dead code.
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Experementing with CISC (x86) I've found that I can achieve an
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order of magintude speed improvement (x3-x5). In the case of RISC
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(sparc) while the performance gain isn't as great it is still
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significant.
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Part One - Static functions: It is possible to control how static
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functions within each module are to be compiled. On a per module
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or global basis, it is possible to specify that a modules static
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functions should be compiled inline. This is controled by the the
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macro's STATIC_INLINE and INLINE_STATIC_<module>.
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Part Two - External functions: Again it is possible to allow the
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inlining of calls to external functions. This is far more
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complicated and much heaver on the compiler. In this case, it is
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controled by the <module>_INLINE macro's. Where each can have a
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value:
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0 Make a normal external call to functions in the module.
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1 Include the module but to not inline functions within it.
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This allows functions within the module to inline functions
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from other modules that have been included.
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2 Both include the module and inline functions contained within
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it.
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Finally, this is not for the faint harted. I've seen GCC get up to
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200mb trying to compile what this can create */
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/* Your compilers inline reserved word */
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#ifndef INLINE
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#if defined(__GNUC__) && defined(__OPTIMIZE__)
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#define INLINE __inline__
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#else
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#define INLINE /*inline*/
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#endif
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#endif
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/* Default prefix for static functions */
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#ifndef STATIC_INLINE
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#define STATIC_INLINE static INLINE
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#endif
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/* Default macro to simplify control several of key the inlines */
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#ifndef DEFAULT_INLINE
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#define DEFAULT_INLINE 0
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#endif
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/* Code that converts between hosts and target byte order. Used on
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every memory access (instruction and data). (See sim-endian.h for
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additional byte swapping configuration information) */
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#ifndef SIM_ENDIAN_INLINE
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#define SIM_ENDIAN_INLINE DEFAULT_INLINE
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#endif
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/* Low level bit manipulation routines used to work around a compiler
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bug in 2.6.3. */
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#ifndef BITS_INLINE
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#define BITS_INLINE DEFAULT_INLINE
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#endif
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/* Code that gives access to various CPU internals such as registers.
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Used every time an instruction is executed */
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#ifndef CPU_INLINE
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#define CPU_INLINE DEFAULT_INLINE
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#endif
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/* Code that translates between an effective and real address. Used
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by every load or store. */
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#ifndef VM_INLINE
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#define VM_INLINE DEFAULT_INLINE
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#endif
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/* Code that loads/stores data to/from the memory data structure.
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Used by every load or store */
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#ifndef CORE_INLINE
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#define CORE_INLINE DEFAULT_INLINE
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#endif
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/* Code to check for and process any events scheduled in the future.
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Called once per instruction cycle */
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#ifndef EVENTS_INLINE
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#define EVENTS_INLINE DEFAULT_INLINE
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#endif
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/* Code monotoring the processors performance. It counts events on
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every instruction cycle */
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#ifndef MON_INLINE
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#define MON_INLINE DEFAULT_INLINE
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#endif
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/* Code called on the rare occasions that an interrupt occures. */
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#ifndef INTERRUPTS_INLINE
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#define INTERRUPTS_INLINE 0
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#endif
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/* Code called on the rare occasion that either gdb or the device tree
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need to manipulate a register within a processor */
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#ifndef REGISTERS_INLINE
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#define REGISTERS_INLINE 0
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#endif
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/* Code called on the rare occasion that a processor is manipulating
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real hardware instead of RAM.
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Also, most of the functions in devices.c are always called through
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a jump table.
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There seems to be some problem with making either device_tree or
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devices inline. It reports the message: device_tree_find_node()
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not a leaf */
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#ifndef DEVICE_TREE_INLINE
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#define DEVICE_TREE_INLINE 0
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#endif
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#ifndef DEVICES_INLINE
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#define DEVICES_INLINE 0
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#endif
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/* Code called whenever information on a Special Purpose Register is
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required. Called by the mflr/mtlr pseudo instructions */
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#ifndef SPREG_INLINE
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#define SPREG_INLINE DEFAULT_INLINE
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#endif
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/* Functions modeling the semantics of each instruction. Two cases to
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consider, firstly of idecode is implemented with a switch then this
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allows the idecode function to inline each semantic function
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(avoiding a call). The second case is when idecode is using a
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table, even then while the semantic functions can't be inlined,
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setting it to one still enables each semantic function to inline
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anything they call (if that code is marked for being inlined).
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WARNING: you need lots (like 200mb of swap) of swap. Setting this
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to 1 is useful when using a table as it enables the sematic code to
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inline all of their called functions */
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#ifndef SEMANTICS_INLINE
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#define SEMANTICS_INLINE (DEFAULT_INLINE ? 1 : 0)
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#endif
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/* Code to decode an instruction. Normally called on every instruction
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cycle */
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#ifndef IDECODE_INLINE
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#define IDECODE_INLINE DEFAULT_INLINE
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#endif
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/* Model specific code used in simulating functional units */
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#ifndef MODEL_INLINE
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#define MODEL_INLINE DEFAULT_INLINE
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#endif
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/* Code to simulate functional units of real machines */
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#ifndef FUNCTION_UNIT_INLINE
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#define FUNCTION_UNIT_INLINE DEFAULT_INLINE
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#endif
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#endif /* _CONFIG_H */
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