317 lines
7.9 KiB
C
317 lines
7.9 KiB
C
/* Lattice Mico32 UART model.
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Contributed by Jon Beniston <jon@beniston.com>
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Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "sim-main.h"
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#include "hw-main.h"
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#include "sim-assert.h"
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#include <stdio.h>
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#include <sys/time.h>
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struct lm32uart
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{
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unsigned base; /* Base address of this UART. */
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unsigned limit; /* Limit address of this UART. */
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unsigned char rbr;
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unsigned char thr;
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unsigned char ier;
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unsigned char iir;
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unsigned char lcr;
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unsigned char mcr;
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unsigned char lsr;
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unsigned char msr;
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unsigned char div;
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struct hw_event *event;
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};
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/* UART registers. */
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#define LM32_UART_RBR 0x0
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#define LM32_UART_THR 0x0
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#define LM32_UART_IER 0x4
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#define LM32_UART_IIR 0x8
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#define LM32_UART_LCR 0xc
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#define LM32_UART_MCR 0x10
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#define LM32_UART_LSR 0x14
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#define LM32_UART_MSR 0x18
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#define LM32_UART_DIV 0x1c
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#define LM32_UART_IER_RX_INT 0x1
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#define LM32_UART_IER_TX_INT 0x2
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#define MICOUART_IIR_TXRDY 0x2
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#define MICOUART_IIR_RXRDY 0x4
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#define LM32_UART_LSR_RX_RDY 0x01
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#define LM32_UART_LSR_TX_RDY 0x20
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#define LM32_UART_LCR_WLS_MASK 0x3
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#define LM32_UART_LCR_WLS_5 0x0
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#define LM32_UART_LCR_WLS_6 0x1
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#define LM32_UART_LCR_WLS_7 0x2
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#define LM32_UART_LCR_WLS_8 0x3
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/* UART ports. */
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enum
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{
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INT_PORT
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};
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static const struct hw_port_descriptor lm32uart_ports[] = {
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{"int", INT_PORT, 0, output_port},
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{}
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};
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static void
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do_uart_tx_event (struct hw *me, void *data)
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{
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struct lm32uart *uart = hw_data (me);
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char c;
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/* Generate interrupt when transmission is complete. */
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if (uart->ier & LM32_UART_IER_TX_INT)
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{
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/* Generate interrupt */
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hw_port_event (me, INT_PORT, 1);
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}
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/* Indicate which interrupt has occured. */
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uart->iir = MICOUART_IIR_TXRDY;
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/* Indicate THR is empty. */
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uart->lsr |= LM32_UART_LSR_TX_RDY;
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/* Output the character in the THR. */
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c = (char) uart->thr;
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/* WLS field in LCR register specifies the number of bits to output. */
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switch (uart->lcr & LM32_UART_LCR_WLS_MASK)
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{
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case LM32_UART_LCR_WLS_5:
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c &= 0x1f;
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break;
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case LM32_UART_LCR_WLS_6:
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c &= 0x3f;
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break;
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case LM32_UART_LCR_WLS_7:
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c &= 0x7f;
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break;
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}
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printf ("%c", c);
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}
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static unsigned
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lm32uart_io_write_buffer (struct hw *me,
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const void *source,
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int space, unsigned_word base, unsigned nr_bytes)
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{
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struct lm32uart *uart = hw_data (me);
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int uart_reg;
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const unsigned char *source_bytes = source;
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int value = 0;
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HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
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(int) nr_bytes, value));
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if (nr_bytes == 4)
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value = (source_bytes[0] << 24)
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| (source_bytes[1] << 16) | (source_bytes[2] << 8) | (source_bytes[3]);
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else
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hw_abort (me, "write of unsupported number of bytes: %d.", nr_bytes);
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uart_reg = base - uart->base;
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switch (uart_reg)
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{
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case LM32_UART_THR:
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/* Buffer the character to output. */
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uart->thr = value;
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/* Indicate the THR is full. */
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uart->lsr &= ~LM32_UART_LSR_TX_RDY;
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/* deassert interrupt when IER is loaded. */
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uart->iir &= ~MICOUART_IIR_TXRDY;
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/* schedule an event to output the character. */
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hw_event_queue_schedule (me, 1, do_uart_tx_event, 0);
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break;
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case LM32_UART_IER:
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uart->ier = value;
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if ((value & LM32_UART_IER_TX_INT)
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&& (uart->lsr & LM32_UART_LSR_TX_RDY))
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{
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/* hw_event_queue_schedule (me, 1, do_uart_tx_event, 0); */
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uart->lsr |= LM32_UART_LSR_TX_RDY;
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uart->iir |= MICOUART_IIR_TXRDY;
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hw_port_event (me, INT_PORT, 1);
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}
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else if ((value & LM32_UART_IER_TX_INT) == 0)
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{
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hw_port_event (me, INT_PORT, 0);
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}
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break;
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case LM32_UART_IIR:
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uart->iir = value;
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break;
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case LM32_UART_LCR:
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uart->lcr = value;
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break;
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case LM32_UART_MCR:
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uart->mcr = value;
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break;
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case LM32_UART_LSR:
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uart->lsr = value;
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break;
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case LM32_UART_MSR:
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uart->msr = value;
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break;
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case LM32_UART_DIV:
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uart->div = value;
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break;
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default:
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hw_abort (me, "write to invalid register address: 0x%x.", uart_reg);
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}
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return nr_bytes;
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}
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static unsigned
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lm32uart_io_read_buffer (struct hw *me,
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void *dest,
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int space, unsigned_word base, unsigned nr_bytes)
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{
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struct lm32uart *uart = hw_data (me);
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int uart_reg;
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int value;
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unsigned char *dest_bytes = dest;
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fd_set fd;
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struct timeval tv;
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HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes));
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uart_reg = base - uart->base;
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switch (uart_reg)
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{
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case LM32_UART_RBR:
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value = getchar ();
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uart->lsr &= ~LM32_UART_LSR_RX_RDY;
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break;
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case LM32_UART_IER:
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value = uart->ier;
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break;
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case LM32_UART_IIR:
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value = uart->iir;
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break;
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case LM32_UART_LCR:
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value = uart->lcr;
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break;
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case LM32_UART_MCR:
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value = uart->mcr;
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break;
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case LM32_UART_LSR:
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/* Check to see if any data waiting in stdin. */
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FD_ZERO (&fd);
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FD_SET (fileno (stdin), &fd);
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tv.tv_sec = 0;
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tv.tv_usec = 1;
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if (select (fileno (stdin) + 1, &fd, NULL, NULL, &tv))
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uart->lsr |= LM32_UART_LSR_RX_RDY;
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value = uart->lsr;
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break;
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case LM32_UART_MSR:
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value = uart->msr;
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break;
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case LM32_UART_DIV:
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value = uart->div;
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break;
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default:
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hw_abort (me, "read from invalid register address: 0x%x.", uart_reg);
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}
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if (nr_bytes == 4)
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{
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dest_bytes[0] = value >> 24;
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dest_bytes[1] = value >> 16;
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dest_bytes[2] = value >> 8;
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dest_bytes[3] = value;
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}
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else
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hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes);
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return nr_bytes;
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}
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static void
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attach_lm32uart_regs (struct hw *me, struct lm32uart *uart)
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{
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unsigned_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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uart->base = attach_address;
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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uart->limit = attach_address + (attach_size - 1);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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}
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static void
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lm32uart_finish (struct hw *me)
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{
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struct lm32uart *uart;
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int i;
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uart = HW_ZALLOC (me, struct lm32uart);
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set_hw_data (me, uart);
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set_hw_io_read_buffer (me, lm32uart_io_read_buffer);
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set_hw_io_write_buffer (me, lm32uart_io_write_buffer);
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set_hw_ports (me, lm32uart_ports);
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/* Attach ourself to our parent bus. */
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attach_lm32uart_regs (me, uart);
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/* Initialize the UART. */
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uart->rbr = 0;
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uart->thr = 0;
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uart->ier = 0;
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uart->iir = 0;
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uart->lcr = 0;
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uart->mcr = 0;
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uart->lsr = LM32_UART_LSR_TX_RDY;
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uart->msr = 0;
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uart->div = 0; /* By setting to zero, characters are output immediately. */
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}
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const struct hw_descriptor dv_lm32uart_descriptor[] = {
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{"lm32uart", lm32uart_finish,},
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{NULL},
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};
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