7cbea0890e
Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
592 lines
14 KiB
C
592 lines
14 KiB
C
// -*- C -*-
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// Simulator definition for the MIPS MDMX ASE.
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// Copyright (C) 2002 Free Software Foundation, Inc.
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// Contributed by Broadcom Corporation (SiByte).
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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// Reference: MIPS64 Architecture Volume IV-b:
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// The MDMX Application-Specific Extension
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// Notes on "format selectors" (FMTSEL):
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//
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// A selector with final bit 0 indicates OB format.
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// A selector with final bits 01 indicates QH format.
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// A selector with final bits 11 has UNPREDICTABLE result per the spec.
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//
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// Similarly, for the single-bit fields which differentiate between
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// formats (FMTOP), 0 is OB format and 1 is QH format.
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// If you change this file to add instructions, please make sure that model
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// "sb1" configurations still build, and that you've added no new
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// instructions to the "sb1" model.
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// Helper:
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//
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// Check whether MDMX is usable, and if not signal an appropriate exception.
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//
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:function:::void:check_mdmx:instruction_word insn
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*mdmx:
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{
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if (! COP_Usable (1))
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SignalExceptionCoProcessorUnusable (1);
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if ((SR & (status_MX|status_FR)) != (status_MX|status_FR))
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SignalExceptionMDMX ();
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check_u64 (SD_, insn);
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}
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// Helper:
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//
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// Check whether a given MDMX format selector indicates a valid and usable
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// format, and if not signal an appropriate exception.
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//
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:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
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*mdmx:
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{
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switch (fmtsel & 0x03)
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{
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case 0x00: /* ob */
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case 0x02:
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case 0x01: /* qh */
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return 1;
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case 0x03: /* UNPREDICTABLE */
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SignalException (ReservedInstruction, insn);
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return 0;
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}
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return 0;
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}
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// Helper:
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//
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// Check whether a given MDMX format bit indicates a valid and usable
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// format, and if not signal an appropriate exception.
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//
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:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
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*mdmx:
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{
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switch (fmtop & 0x01)
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{
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case 0x00: /* ob */
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case 0x01: /* qh */
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return 1;
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}
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return 0;
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}
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:%s::::FMTSEL:int fmtsel
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*mdmx:
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*sb1:
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{
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if ((fmtsel & 0x1) == 0)
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return "ob";
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else if ((fmtsel & 0x3) == 1)
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return "qh";
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else
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return "?";
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}
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:%s::::FMTOP:int fmtop
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*mdmx:
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*sb1:
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{
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switch (fmtop)
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{
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case 0: return "ob";
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case 1: return "qh";
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default: return "?";
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}
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}
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:%s::::SHOP:int shop
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*mdmx:
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*sb1:
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{
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if ((shop & 0x11) == 0x00)
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switch ((shop >> 1) & 0x07)
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{
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case 3: return "upsl.ob";
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case 4: return "pach.ob";
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case 6: return "mixh.ob";
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case 7: return "mixl.ob";
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default: return "?";
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}
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else if ((shop & 0x03) == 0x01)
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switch ((shop >> 2) & 0x07)
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{
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case 0: return "mixh.qh";
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case 1: return "mixl.qh";
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case 2: return "pach.qh";
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case 4: return "bfla.qh";
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case 6: return "repa.qh";
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case 7: return "repb.qh";
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default: return "?";
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}
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else
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return "?";
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt
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"add.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Add(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt
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"adda.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_AddA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt
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"addl.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_AddL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt
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"alni.%s<FMTOP> v<VD>, v<VS>, v<VT>, <IMM>"
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*mdmx:
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*sb1:
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{
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unsigned64 result;
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int s;
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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s = (IMM << 3);
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result = ValueFPR(VS,fmt_mdmx) << s;
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if (s != 0) // x86 gcc treats >> 64 as >> 0
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result |= ValueFPR(VT,fmt_mdmx) >> (64 - s);
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StoreFPR(VD,fmt_mdmx,result);
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}
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011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt
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"alnv.%s<FMTOP> v<VD>, v<VS>, v<VT>, r<RS>"
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*mdmx:
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*sb1:
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{
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unsigned64 result;
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int s;
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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s = ((GPR[RS] & 0x7) << 3);
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result = ValueFPR(VS,fmt_mdmx) << s;
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if (s != 0) // x86 gcc treats >> 64 as >> 0
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result |= ValueFPR(VT,fmt_mdmx) >> (64 - s);
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StoreFPR(VD,fmt_mdmx,result);
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt
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"and.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_And(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt
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"c.eq.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_EQ,VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt
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"c.le.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT|MX_C_EQ,VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt
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"c.lt.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT,VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt
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"max.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Max(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt
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"min.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Min(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,3.SEL,01,5.VT,5.VS,5.VD,000000:MDMX:64::MSGN.QH
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"msgn.qh v<VD>, v<VS>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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StoreFPR(VD,fmt_mdmx,MX_Msgn(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL)));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt
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"mul.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Mul(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt
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"mula.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt
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"mull.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt
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"muls.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulS(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt
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"mulsl.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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MX_MulSL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt
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"nor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Nor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt
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"or.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Or(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt
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"pickf.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Pick(0,ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt
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"pickt.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_Pick(1,ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
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}
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011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt
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"rach.%s<FMTOP> v<VD>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_H,FMTOP));
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}
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011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt
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"racl.%s<FMTOP> v<VD>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_L,FMTOP));
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}
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011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt
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"racm.%s<FMTOP> v<VD>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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check_mdmx_fmtop (SD_, instruction_0, FMTOP);
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StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_M,FMTOP));
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}
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011110,3.SEL,01,5.VT,00000,5.VD,100101:MDMX:64::RNAS.QH
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"rnas.qh v<VD>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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StoreFPR(VD,fmt_mdmx,MX_RNAS(VT,qh_fmtsel(SEL)));
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}
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011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt
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"rnau.%s<FMTSEL> v<VD>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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StoreFPR(VD,fmt_mdmx,MX_RNAU(VT,FMTSEL));
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}
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011110,3.SEL,01,5.VT,00000,5.VD,100110:MDMX:64::RNES.QH
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"rnes.qh v<VD>, v<VT>"
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*mdmx:
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{
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check_mdmx (SD_, instruction_0);
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StoreFPR(VD,fmt_mdmx,MX_RNES(VT,qh_fmtsel(SEL)));
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}
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011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt
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"rneu.%s<FMTSEL> v<VD>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
StoreFPR(VD,fmt_mdmx,MX_RNEU(VT,FMTSEL));
|
|
}
|
|
|
|
|
|
011110,3.SEL,01,5.VT,00000,5.VD,100100:MDMX:64::RZS.QH
|
|
"rzs.qh v<VD>, v<VT>"
|
|
*mdmx:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
StoreFPR(VD,fmt_mdmx,MX_RZS(VT,qh_fmtsel(SEL)));
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt
|
|
"rzu.%s<FMTSEL> v<VD>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
StoreFPR(VD,fmt_mdmx,MX_RZU(VT,FMTSEL));
|
|
}
|
|
|
|
|
|
011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt
|
|
"shfl.%s<SHOP> v<VD>, v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, SHOP))
|
|
StoreFPR(VD,fmt_mdmx,MX_SHFL(SHOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx)));
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt
|
|
"sll.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
StoreFPR(VD,fmt_mdmx,MX_ShiftLeftLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
|
}
|
|
|
|
|
|
011110,3.SEL,01,5.VT,5.VS,5.VD,010011:MDMX:64::SRA.QH
|
|
"sra.qh v<VD>, v<VS>, v<VT>"
|
|
*mdmx:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
StoreFPR(VD,fmt_mdmx,MX_ShiftRightArith(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL)));
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt
|
|
"srl.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
StoreFPR(VD,fmt_mdmx,MX_ShiftRightLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt
|
|
"sub.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
StoreFPR(VD,fmt_mdmx,MX_Sub(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt
|
|
"suba.%s<FMTSEL> v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
MX_SubA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt
|
|
"subl.%s<FMTSEL> v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
MX_SubL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
|
|
}
|
|
|
|
|
|
011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt
|
|
"wach.%s<FMTOP> v<VS>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
|
MX_WACH(FMTOP,ValueFPR(VS,fmt_mdmx));
|
|
}
|
|
|
|
|
|
011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt
|
|
"wacl.%s<FMTOP> v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
|
MX_WACL(FMTOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx));
|
|
}
|
|
|
|
|
|
011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt
|
|
"xor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
|
*mdmx:
|
|
*sb1:
|
|
{
|
|
check_mdmx (SD_, instruction_0);
|
|
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
|
StoreFPR(VD,fmt_mdmx,MX_Xor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
|
}
|