351 lines
14 KiB
C
351 lines
14 KiB
C
/* Target machine sub-parameters for SPARC64, for GDB, the GNU debugger.
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This is included by other tm-*.h files to define SPARC cpu-related info.
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Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
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This is (obviously) based on the SPARC Vn (n<9) port.
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Contributed by Doug Evans (dje@cygnus.com).
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "sparc/tm-sparc.h"
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/* We have long longs. */
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#define LONG_LONG
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/* When passing a structure to a function, Sun cc passes the address
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in a register, not the structure itself. It (under SunOS4) creates
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two symbols, so we get a LOC_ARG saying the address is on the stack
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(a lie, and a serious one since we don't know which register to
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use), and a LOC_REGISTER saying that the struct is in a register
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(sort of a lie, but fixable with REG_STRUCT_HAS_ADDR). Gcc version
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two (as of 1.92) behaves like sun cc. REG_STRUCT_HAS_ADDR is smart
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enough to distinguish between Sun cc, gcc version 1 and gcc version 2.
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This still doesn't work if the argument is not one passed in a
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register (i.e. it's the 7th or later argument). */
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#undef REG_STRUCT_HAS_ADDR
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#define REG_STRUCT_HAS_ADDR(gcc_p) (gcc_p != 1)
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#undef STRUCT_ARG_SYM_GARBAGE
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#define STRUCT_ARG_SYM_GARBAGE(gcc_p) (gcc_p != 1)
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/* Stack has strict alignment. */
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#undef STACK_ALIGN
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#define STACK_ALIGN(ADDR) (((ADDR)+15)&-16)
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/* Nonzero if instruction at PC is a return instruction. */
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/* For SPARC, this is either a "jmpl %o7+8,%g0" or "jmpl %i7+8,%g0".
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Note: this does not work for functions returning structures under SunOS.
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This should work for v9, however. */
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#undef ABOUT_TO_RETURN
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#define ABOUT_TO_RETURN(pc) \
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((read_memory_integer (pc, 4)|0x00040000) == 0x81c7e008)
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/* Say how long (ordinary) registers are. */
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#undef REGISTER_TYPE
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#define REGISTER_TYPE long long
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/* Number of machine registers */
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#undef NUM_REGS
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#define NUM_REGS 127
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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/* Some of these registers are only accessible from priviledged mode.
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They are here for kernel debuggers, etc. */
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/* FIXME: icc and xcc are currently considered separate registers.
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This may have to change and consider them as just one (ccr).
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Let's postpone this as long as we can. */
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/* FIXME: fcc0-3 are currently separate, even though they are also part of
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fsr. May have to remove them but let's postpone this as long as
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possible. */
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/* FIXME: cle and tle are new registers that haven't entered the docs yet.
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They stand for "current little endian format" and "trap little endian
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format". */
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#undef REGISTER_NAMES
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#define REGISTER_NAMES \
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{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
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"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", \
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
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"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", \
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\
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
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"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", \
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"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", \
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\
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"ccr", "y", "pc", "npc", "asi", "cle", "tle", \
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"fsr", "fprs", "ver", "tick", "pil", "pstate", "wstate", \
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"tba", "tl", "tt", "tpc", "tnpc", "tstate", \
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"cwp", "cansave", "canrestore", "cleanwin", "otherwin", \
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"asr16", "asr17", "asr18", "asr19", "asr20", "asr21", \
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"asr22", "asr23", "asr24", "asr25", "asr26", "asr27", \
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"asr28", "asr29", "asr30", "asr31", \
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/* These are here at the end to simplify removing them if we have to. */ \
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"icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3" \
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}
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/* Register numbers of various important registers.
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Note that some of these values are "real" register numbers,
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and correspond to the general registers of the machine,
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and some are "phony" register numbers which are too large
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to be actual register numbers as far as the user is concerned
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but do serve to get the desired values when passed to read_register. */
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#if 0 /* defined in tm-sparc.h, replicated for doc purposes */
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#define G0_REGNUM 0 /* %g0 */
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#define G1_REGNUM 1 /* %g1 */
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#define O0_REGNUM 8 /* %o0 */
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#define SP_REGNUM 14 /* Contains address of top of stack, \
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which is also the bottom of the frame. */
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#define RP_REGNUM 15 /* Contains return address value, *before* \
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any windows get switched. */
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#define O7_REGNUM 15 /* Last local reg not saved on stack frame */
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#define L0_REGNUM 16 /* First local reg that's saved on stack frame
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rather than in machine registers */
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#define I0_REGNUM 24 /* %i0 */
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#define FP_REGNUM 30 /* Contains address of executing stack frame */
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#define I7_REGNUM 31 /* Last local reg saved on stack frame */
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#define FP0_REGNUM 32 /* Floating point register 0 */
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#endif
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#define FP_MAX_REGNUM 80 /* 1 + last fp reg number */
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/* #undef v8 misc. regs */
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#undef Y_REGNUM
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#undef PS_REGNUM
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#undef WIM_REGNUM
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#undef TBR_REGNUM
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#undef PC_REGNUM
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#undef NPC_REGNUM
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#undef FPS_REGNUM
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#undef CPS_REGNUM
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/* v9 misc. and priv. regs */
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#define C0_REGNUM 80 /* Start of control registers */
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#define CCR_REGNUM (C0_REGNUM + 0) /* Condition Code Register (%xcc,%icc) */
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#define Y_REGNUM (C0_REGNUM + 1) /* Temp register for multiplication, etc. */
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#define PC_REGNUM (C0_REGNUM + 2) /* floating point condition code reg 2 */
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#define NPC_REGNUM (C0_REGNUM + 3) /* floating point condition code reg 2 */
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#define ASI_REGNUM (C0_REGNUM + 4) /* Alternate Space Identifier */
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#define CLE_REGNUM (C0_REGNUM + 5) /* Current Little Endian format */
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#define TLE_REGNUM (C0_REGNUM + 6) /* Trap Little Endian format */
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#define FSR_REGNUM (C0_REGNUM + 7) /* Floating Point State */
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#define FPRS_REGNUM (C0_REGNUM + 8) /* Floating Point Registers State */
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#define VER_REGNUM (C0_REGNUM + 9) /* Version register */
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#define TICK_REGNUM (C0_REGNUM + 10) /* Tick register */
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#define PIL_REGNUM (C0_REGNUM + 11) /* Processor Interrupt Level */
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#define PSTATE_REGNUM (C0_REGNUM + 12) /* Processor State */
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#define WSTATE_REGNUM (C0_REGNUM + 13) /* Window State */
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#define TBA_REGNUM (C0_REGNUM + 14) /* floating point condition code reg 3 */
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#define TL_REGNUM (C0_REGNUM + 15) /* Trap Level */
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#define TT_REGNUM (C0_REGNUM + 16) /* Trap Type */
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#define TPC_REGNUM (C0_REGNUM + 17) /* Trap pc */
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#define TNPC_REGNUM (C0_REGNUM + 18) /* Trap npc */
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#define TSTATE_REGNUM (C0_REGNUM + 19) /* Trap State */
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#define CWP_REGNUM (C0_REGNUM + 20) /* Current Window Pointer */
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#define CANSAVE_REGNUM (C0_REGNUM + 21) /* Savable Windows */
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#define CANRESTORE_REGNUM (C0_REGNUM + 22) /* Restorable Windows */
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#define CLEANWIN_REGNUM (C0_REGNUM + 23) /* Clean Windows */
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#define OTHERWIN_REGNUM (C0_REGNUM + 24) /* Other Windows */
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#define ASR_REGNUM(n) (C0_REGNUM+(25-16)+(n)) /* Ancillary State Register
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(n = 16...31) */
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#define ICC_REGNUM (C0_REGNUM + 41) /* 32 bit condition codes */
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#define XCC_REGNUM (C0_REGNUM + 42) /* 64 bit condition codes */
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#define FCC0_REGNUM (C0_REGNUM + 43) /* floatpoint condition code reg 0 */
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#define FCC1_REGNUM (C0_REGNUM + 44) /* floating point condition code reg 0 */
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#define FCC2_REGNUM (C0_REGNUM + 45) /* floating point condition code reg 1 */
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#define FCC3_REGNUM (C0_REGNUM + 46) /* floating point condition code reg 2 */
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/* FIXME: PS_REGNUM, FPS_REGNUM, CPS_REGNUM are for priviledged v8 registers
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which don't exist in v9 (in the same form). We use bits of sparc-tdep.c
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which requires these, so define them here to be unused ASR regs so
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sparc-tdep.c will compile. What we really want to do is put some
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conditionals in sparc-tdep.c (run time or compile time) or separate the v8
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stuff out of sparc-tdep.c. */
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#define PS_REGNUM (ASR_REGNUM (29))
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#define FPS_REGNUM (ASR_REGNUM (30))
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#define CPS_REGNUM (ASR_REGNUM (31))
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'.
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Some of the registers aren't 64 bits, but it's a lot simpler just to assume
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they all are (since most of them are). */
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#undef REGISTER_BYTES
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#define REGISTER_BYTES (32*8+32*8+47*8)
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/* Index within `registers' of the first byte of the space for
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register N. */
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#undef REGISTER_BYTE
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#define REGISTER_BYTE(N) \
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((N) < 32 ? (N)*8 \
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: (N) < 64 ? 32*8 + ((N)-32)*4 \
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: (N) < C0_REGNUM ? 32*8 + 32*4 + ((N)-64)*8 \
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: 64*8 + ((N)-C0_REGNUM)*8)
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/* Number of bytes of storage in the actual machine representation
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for register N. */
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#undef REGISTER_RAW_SIZE
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#define REGISTER_RAW_SIZE(N) (8)
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/* Number of bytes of storage in the program's representation
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for register N. */
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#undef REGISTER_VIRTUAL_SIZE
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#define REGISTER_VIRTUAL_SIZE(N) (8)
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/* Largest value REGISTER_RAW_SIZE can have. */
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/* tm-sparc.h defines this as 8, but play it safe. */
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#undef MAX_REGISTER_RAW_SIZE
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#define MAX_REGISTER_RAW_SIZE (8)
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/* Largest value REGISTER_VIRTUAL_SIZE can have. */
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/* tm-sparc.h defines this as 8, but play it safe. */
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#undef MAX_REGISTER_VIRTUAL_SIZE
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#define MAX_REGISTER_VIRTUAL_SIZE (8)
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/* Convert data from raw format for register REGNUM
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to virtual format for register REGNUM. */
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/* ??? Remove when tm-sparc.h is fixed. */
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#undef REGISTER_CONVERT_TO_VIRTUAL
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#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,FROM,TO) \
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{ memcpy ((TO), (FROM), REGISTER_RAW_SIZE (0)); }
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/* Convert data from virtual format for register REGNUM
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to raw format for register REGNUM. */
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/* ??? Remove when tm-sparc.h is fixed. */
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#undef REGISTER_CONVERT_TO_RAW
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#define REGISTER_CONVERT_TO_RAW(REGNUM,FROM,TO) \
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{ memcpy ((TO), (FROM), REGISTER_RAW_SIZE (0)); }
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/* Return the GDB type object for the "standard" data type
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of data in register N. */
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#undef REGISTER_VIRTUAL_TYPE
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#define REGISTER_VIRTUAL_TYPE(N) \
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((N) < 32 ? builtin_type_long_long : (N) < 80 ? builtin_type_float : \
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builtin_type_long_long)
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/* We use to support both 32 bit and 64 bit pointers.
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We can't anymore because TARGET_PTR_BIT must now be a constant. */
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#undef TARGET_PTR_BIT
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#define TARGET_PTR_BIT 64
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/* Store the address of the place in which to copy the structure the
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subroutine will return. This is called from call_function. */
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/* FIXME: V9 uses %o0 for this. */
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#undef STORE_STRUCT_RETURN
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#define STORE_STRUCT_RETURN(ADDR, SP) \
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{ target_write_memory ((SP)+(16*8), (char *)&(ADDR), 8); }
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/* Extract from an array REGBUF containing the (raw) register state
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a function return value of type TYPE, and copy that, in virtual format,
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into VALBUF. */ /* FIXME */
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#undef EXTRACT_RETURN_VALUE
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#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
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{ \
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if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) \
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{ \
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memcpy ((VALBUF), ((int *)(REGBUF))+FP0_REGNUM, TYPE_LENGTH(TYPE));\
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} \
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else \
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memcpy ((VALBUF), \
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(char *)(REGBUF) + 8 * 8 + \
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(TYPE_LENGTH(TYPE) >= 8 ? 0 : 8 - TYPE_LENGTH(TYPE)), \
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TYPE_LENGTH(TYPE)); \
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}
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/* Extract from an array REGBUF containing the (raw) register state
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the address in which a function should return its structure value,
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as a CORE_ADDR (or an expression that can be used as one). */
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#undef EXTRACT_STRUCT_VALUE_ADDRESS
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
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(sparc64_extract_struct_value_address (REGBUF))
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extern CORE_ADDR
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sparc64_extract_struct_value_address PARAMS ((char [REGISTER_BYTES]));
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/* Return number of bytes at start of arglist that are not really args. */
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#undef FRAME_ARGS_SKIP
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#define FRAME_ARGS_SKIP 136
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/* Sparc has no reliable single step ptrace call */
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#undef NO_SINGLE_STEP
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#define NO_SINGLE_STEP 1
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extern void single_step ();
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/* We need two arguments (in general) to the "info frame" command.
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Note that the definition of this macro implies that there exists a
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function "setup_arbitrary_frame" in sparc-tdep.c */
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#undef SETUP_ARBITRARY_FRAME /*FIXME*/
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#undef FRAME_SPECIFICATION_DYADIC
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#define FRAME_SPECIFICATION_DYADIC
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/* To print every pair of float registers as a double, we use this hook.
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We also print the condition code registers in a readable format
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(FIXME: can expand this to all control regs). */
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#undef PRINT_REGISTER_HOOK
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#define PRINT_REGISTER_HOOK(regno) \
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sparc_print_register_hook (regno)
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/* Offsets into jmp_buf.
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FIXME: This was borrowed from the v8 stuff and will probably have to change
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for v9. */
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#define JB_ELEMENT_SIZE 8 /* Size of each element in jmp_buf */
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#define JB_ONSSTACK 0
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#define JB_SIGMASK 1
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#define JB_SP 2
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#define JB_PC 3
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#define JB_NPC 4
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#define JB_PSR 5
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#define JB_G1 6
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#define JB_O0 7
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#define JB_WBCNT 8
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/* Figure out where the longjmp will land. We expect that we have just entered
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longjmp and haven't yet setup the stack frame, so the args are still in the
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output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
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extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
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This routine returns true on success */
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extern int
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get_longjmp_target PARAMS ((CORE_ADDR *));
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#define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
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