cdc83fba73
* elf32-spu.c (build_stub): Always build "compact" sofware i-cache stubs. ld/ * emultempl/spuelf.em (PARSE_AND_LIST_ARGS_CASES): Always use compact stubs with software i-cache. ld/testsuite/ * ld-spu/icache1.d: Update for compact stubs.
172 lines
3.9 KiB
Makefile
172 lines
3.9 KiB
Makefile
#source: icache1.s
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#ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
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#objdump: -D
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.* elf32-spu
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Disassembly of section .ovl.init:
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00000000 <__icache_fileoff>:
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.* 00 00 00 00.*
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.* 00 00 02 00.*
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\.\.\.
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Disassembly of section \.ovly1:
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00000000 <\.ovly1>:
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.* ai \$1,\$1,64 # 40
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.* lqd \$0,16\(\$1\)
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.* bi \$0
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\.\.\.
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Disassembly of section \.ovly2:
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00000400 <f1>:
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.* 40 20 00 00 nop \$0
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.* 24 00 40 80 stqd \$0,16\(\$1\)
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.* 1c f0 00 81 ai \$1,\$1,-64
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.* 24 00 00 81 stqd \$1,0\(\$1\)
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.* 33 00 78 80 brsl \$0,7d4 .*
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.* 33 00 7a 00 brsl \$0,7e4 .*
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\.\.\.
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.* 32 00 17 80 br 7f4 .*
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\.\.\.
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7d0: 00 04 09 04.*
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7d4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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7d8: a0 00 04 10.*
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7dc: 00 00 e6 00.*
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7e0: 00 04 08 00.*
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7e4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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7e8: a0 00 04 14.*
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7ec: 00 00 07 80.*
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7f0: 00 04 00 00.*
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7f4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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7f8: 20 00 07 38.*
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7fc: 00 7f 0e 80.*
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Disassembly of section \.ovly3:
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00000800 <f3>:
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\.\.\.
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.* 35 00 00 00 bi \$0
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00000904 <f2>:
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.* 1c e0 00 81 ai \$1,\$1,-128
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.* 24 00 00 81 stqd \$1,0\(\$1\)
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\.\.\.
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.* 1c 20 00 81 ai \$1,\$1,128 # 80
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.* 35 00 00 00 bi \$0
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\.\.\.
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Disassembly of section \.ovly4:
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00000c00 <f5>:
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.* 24 00 40 80 stqd \$0,16\(\$1\)
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.* 24 f8 00 81 stqd \$1,-512\(\$1\)
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.* 1c 80 00 81 ai \$1,\$1,-512
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.* 33 7f fe 80 brsl \$0,c00 <f5> # c00
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\.\.\.
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.* 42 01 00 03 ila \$3,200.*
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.* 18 00 c0 81 a \$1,\$1,\$3
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.* 34 00 40 80 lqd \$0,16\(\$1\)
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.* 35 00 00 00 bi \$0
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\.\.\.
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Disassembly of section \.ovly5:
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00000000 <\.ovly5>:
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\.\.\.
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.* 42 01 00 03 ila \$3,200 .*
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.* 18 00 c0 81 a \$1,\$1,\$3
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.* 34 00 40 80 lqd \$0,16\(\$1\)
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.* 30 00 7e 80 bra 3f4 .*
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\.\.\.
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3f0: 00 04 0c 00.*
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3f4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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3f8: a0 00 03 2c.*
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3fc: 00 01 fe 80.*
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Disassembly of section \.ovly6:
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00000400 <\.ovly6>:
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.* 31 00 fa 80 brasl \$0,7d4 .*
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.* 33 00 7c 00 brsl \$0,7e4 .*
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\.\.\.
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.* 32 00 19 80 br 7f4 .*
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\.\.\.
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7d0: 00 08 0c 00.*
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7d4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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7d8: a0 00 04 00.*
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7dc: 00 01 7a 80.*
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7e0: 00 08 0c 00.*
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7e4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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7e8: a0 00 04 04.*
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7ec: 00 00 83 80.*
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7f0: 00 08 00 00.*
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7f4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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7f8: 20 00 07 28.*
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7fc: 00 7f 02 80.*
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Disassembly of section \.ovly7:
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00000800 <\.ovly7>:
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.* 41 7f ff 83 ilhu \$3,65535 # ffff
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.* 60 f8 30 03 iohl \$3,61536 # f060
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.* 18 00 c0 84 a \$4,\$1,\$3
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.* 00 20 00 00 lnop
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.* 04 00 02 01 ori \$1,\$4,0
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.* 24 00 02 04 stqd \$4,0\(\$4\)
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.* 33 00 77 80 brsl \$0,bd4 .*
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.* 33 00 79 00 brsl \$0,be4 .*
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.* 34 00 00 81 lqd \$1,0\(\$1\)
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\.\.\.
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.* 32 00 16 00 br bf4 .*
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\.\.\.
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bd0: 00 04 0c 00.*
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bd4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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bd8: a0 00 08 18.*
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bdc: 00 00 0a 80.*
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be0: 00 08 0c 00.*
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be4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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be8: a0 00 08 1c.*
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bec: 00 00 05 80.*
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bf0: 00 08 04 00.*
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bf4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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bf8: 20 00 0b 44.*
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bfc: 00 7f 01 80.*
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Disassembly of section \.ovly8:
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00000c00 <f4>:
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.* 24 00 40 80 stqd \$0,16\(\$1\)
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.* 24 f8 00 81 stqd \$1,-512\(\$1\)
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.* 1c 80 00 81 ai \$1,\$1,-512
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.* 31 01 fc 80 brasl \$0,fe4 .*
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\.\.\.
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.* 32 00 18 80 br ff4 .*
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\.\.\.
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fe0: 00 04 09 04.*
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fe4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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fe8: a0 00 0c 0c.*
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fec: 00 00 dc 00.*
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ff0: 00 08 08 00.*
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ff4: 31 02 01 cb brasl \$75,100c <__icache_br_handler>
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ff8: 20 00 0f 30.*
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ffc: 00 7f 02 80.*
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Disassembly of section \.text:
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00001000 <_start>:
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.* 41 00 02 03 ilhu \$3,4
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.* 60 86 00 03 iohl \$3,3072 # c00
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.* 32 00 03 80 br 1024.*
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0000100c <__icache_br_handler>:
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100c: 00 00 00 00 stop
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00001010 <__icache_call_handler>:
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\.\.\.
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1020: 00 04 04 00.*
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1024: 31 02 02 4b brasl \$75,1010 <__icache_call_handler>
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1028: a0 00 10 08.*
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102c: 00 7e 7c 80.*
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#pass
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