49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
/* Sparc target configuration file. -*- C -*- */
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#ifndef SPARC_TCONFIG_H
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#define SPARC_TCONFIG_H
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/* See sim-hload.c. We properly handle LMA. */
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#define SIM_HANDLES_LMA 1
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/* Device support. FIXME: revisit. */
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#define WITH_DEVICES 1
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/* This is a global setting. Different cpu families can't mix-n-match -scache
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and -pbb. However some cpu families may use -simple while others use
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one of -scache/-pbb. */
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#define WITH_SCACHE_PBB 0
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/* Simple-engine branch support.
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Delay slots, annuling, and traps are (currently) handled by using the
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simple engine and doing all the work in SEM_{,N}BRANCH_FINI. */
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#define TARGET_SEM_BRANCH_FINI(vpc, bool_attrs, taken_p) \
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do { \
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IADDR npc = GET_H_NPC (); \
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if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_DELAY_SLOT) && taken_p) \
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{ \
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SET_H_PC (npc); \
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SET_H_NPC (vpc); \
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} \
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else if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_TRAP) && taken_p) \
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{ \
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SET_H_PC (vpc); \
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SET_H_NPC ((vpc) + 4); \
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} \
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else \
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{ \
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SET_H_PC (npc); \
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SET_H_NPC (npc + 4); \
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} \
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} while (0)
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#define TARGET_SEM_NBRANCH_FINI(vpc, bool_attrs) \
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do { \
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IADDR npc = GET_H_NPC (); \
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SET_H_PC (npc); \
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SET_H_NPC (npc + 4); \
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} while (0)
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#endif /* SPARC_TCONFIG_H */
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