91 lines
3.2 KiB
C
91 lines
3.2 KiB
C
/* sparc32 register definitions
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Copyright (C) 1999 Cygnus Solutions. */
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#ifndef REG32_H
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#define REG32_H
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/* PSR bits */
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#define PSR_IMPL 0xf0000000
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#define PSR_VER 0x0f000000
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#define PSR_CC 0x00f00000
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#define PSR_N 0x00800000
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#define PSR_Z 0x00400000
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#define PSR_V 0x00200000
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#define PSR_C 0x00100000
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#define PSR_EC 0x00002000
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#define PSR_EF 0x00001000
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#define PSR_PIL 0x00000f00
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#define PSR_S 0x00000080
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#define PSR_PS 0x00000040
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#define PSR_ET 0x00000020
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#define PSR_CWP 0x0000001f
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/* The PSR is a hodge-podge of various things.
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??? The final organization of this is wip. */
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extern USI sparc32_get_h_psr_handler (SIM_CPU *);
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extern void sparc32_set_h_psr_handler (SIM_CPU *, USI);
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#define GET_H_PSR() sparc32_get_h_psr_handler (current_cpu)
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#define SET_H_PSR(val) sparc32_set_h_psr_handler (current_cpu, (val))
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/* The y reg is a virtual reg as it's actually one of the asr regs.
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??? To be replaced in time with get/set specs. */
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#if 0
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#define sparc32_h_y_get(cpu) (CPU_CGEN_HW (cpu)->h_asr[0])
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#define sparc32_h_y_set(cpu,val) (CPU_CGEN_HW (cpu)->h_asr[0] = (val))
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#endif
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#define GET_H_Y() (CPU (h_asr) [0])
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#define SET_H_Y(newval) do { CPU (h_asr) [0] = (newval); } while (0)
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/* The Trap Base Register. */
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#define GET_H_TBR() CPU (h_tbr)
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#define SET_H_TBR(newval) \
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do { \
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CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000); \
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} while (0)
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/* sparc32 register window stuff. */
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/* Handle gets/sets of h-cwp.
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This handles swapping out the current set of window registers
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and swapping in the new. How the "swapping" is done depends on the
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register window implementation of the day. */
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void sparc32_set_h_cwp_handler (SIM_CPU *, int);
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#define GET_H_CWP() CPU (h_cwp)
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#define SET_H_CWP(newval) sparc32_set_h_cwp_handler (current_cpu, (newval))
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/* WIM accessors. */
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/* ??? Yes, mask computation assumes nwindows < 32. */
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#define GET_H_WIM() (CPU (h_wim) & ((1 << GET_NWINDOWS ()) - 1))
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#define SET_H_WIM(newval) (CPU (h_wim) = (newval))
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/* Return non-zero if window WIN is valid in WIM. */
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#define WINDOW_VALID_P(win, wim) (((wim) & (1 << (win))) == 0)
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void sparc32_alloc_regwins (SIM_CPU *, int);
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void sparc32_free_regwins (SIM_CPU *);
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void sparc32_swapout_regwin (SIM_CPU *, int);
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void sparc32_swapin_regwin (SIM_CPU *, int);
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void sparc32_load_regwin (SIM_CPU *, IADDR pc_, int win_);
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void sparc32_flush_regwin (SIM_CPU *, IADDR pc_, int win_, int no_errors_p_);
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void sparc32_flush_regwins (SIM_CPU *, IADDR pc_, int no_errors_p_);
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void sparc32_save_regwin (SIM_CPU *);
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void sparc32_restore_regwin (SIM_CPU *);
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/* Integer register access macros.
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Provides an interface between the cpu description and the register window
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implementation of the day. To be solidified in time. */
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#define GET_H_GR(r) (current_cpu->current_regs[r])
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/* ??? The r != 0 test may not be necessary as sufficient numbers of dni
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entries can prevent this from occuring (I think). Even then though doing
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this makes things more robust, and a lot of dni's would be needed.
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??? The other way to handle %g0 is to always reset it for each insn
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[perhaps optimized to only do so when necessary]. */
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#define SET_H_GR(r, val) \
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((r) != 0 ? (current_cpu->current_regs[r] = (val)) : 0)
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#endif /* REG32_H */
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