271 lines
8.2 KiB
C
271 lines
8.2 KiB
C
/* Table of opcodes for the AMD 29000
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Copyright (C) 1990, 1991 Free Software Foundation, Inc.
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Contributed by Cygnus Support. Written by Jim Kingdon.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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struct am29k_opcode {
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/* Name of the instruction. */
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char *name;
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/* Opcode (i.e. most significant byte of the word). */
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unsigned char opcode;
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/* A string of characters which describe the operands.
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Valid characters are:
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, Itself. The character appears in the assembly code.
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a RA. The register number is in bits 8-15 of the instruction.
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b RB. The register number is in bits 0-7 of the instruction.
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c RC. The register number is in bits 16-23 of the instruction.
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i An immediate operand is in bits 0-7 of the instruction.
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x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
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(respectively) of the immediate operand.
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h Same as x but the instruction contains bits 16-31 of the
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immediate operand.
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X Same as x but bits 16-31 of the signed immediate operand
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are set to 1 (thus the operand is always negative).
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P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
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(respectively) of the immediate operand.
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P=PC-relative, sign-extended to 32 bits.
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A=Absolute, zero-extended to 32 bits.
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e CE bit (bit 23) for a load/store instruction.
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n Control field (bits 16-22) for a load/store instruction.
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v Immediate operand in bits 16-23 of the instruction.
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(used for trap numbers).
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s SA. Special-purpose register number in bits 8-15
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of the instruction.
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u UI--bit 7 of the instruction.
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r RND--bits 4-6 of the instruction.
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d FD--bits 2-3 of the instruction.
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f FS--bits 0-1 of the instruction. */
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char *args;
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};
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static struct am29k_opcode am29k_opcodes[] =
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{
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{ "add", 0x14, "c,a,b" },
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{ "add", 0x15, "c,a,i" },
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{ "addc", 0x1c, "c,a,b" },
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{ "addc", 0x1d, "c,a,i" },
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{ "addcs", 0x18, "c,a,b" },
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{ "addcs", 0x19, "c,a,i" },
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{ "addcu", 0x1a, "c,a,b" },
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{ "addcu", 0x1b, "c,a,i" },
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{ "adds", 0x10, "c,a,b" },
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{ "adds", 0x11, "c,a,i" },
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{ "addu", 0x12, "c,a,b" },
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{ "addu", 0x13, "c,a,i" },
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{ "and", 0x90, "c,a,b" },
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{ "and", 0x91, "c,a,i" },
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{ "andn", 0x9c, "c,a,b" },
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{ "andn", 0x9d, "c,a,i" },
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{ "aseq", 0x70, "v,a,b" },
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{ "aseq", 0x71, "v,a,i" },
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{ "asge", 0x5c, "v,a,b" },
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{ "asge", 0x5d, "v,a,i" },
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{ "asgeu", 0x5e, "v,a,b" },
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{ "asgeu", 0x5f, "v,a,i" },
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{ "asgt", 0x58, "v,a,b" },
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{ "asgt", 0x59, "v,a,i" },
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{ "asgtu", 0x5a, "v,a,b" },
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{ "asgtu", 0x5b, "v,a,i" },
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{ "asle", 0x54, "v,a,b" },
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{ "asle", 0x55, "v,a,i" },
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{ "asleu", 0x56, "v,a,b" },
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{ "asleu", 0x57, "v,a,i" },
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{ "aslt", 0x50, "v,a,b" },
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{ "aslt", 0x51, "v,a,i" },
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{ "asltu", 0x52, "v,a,b" },
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{ "asltu", 0x53, "v,a,i" },
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{ "asneq", 0x72, "v,a,b" },
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{ "asneq", 0x73, "v,a,i" },
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{ "call", 0xa8, "a,P" },
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{ "call", 0xa9, "a,A" },
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{ "calli", 0xc8, "a,b" },
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{ "class", 0xe6, "c,a,f" },
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{ "clz", 0x08, "c,b" },
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{ "clz", 0x09, "c,i" },
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{ "const", 0x03, "a,x" },
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{ "consth", 0x02, "a,h" },
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{ "consthz", 0x05, "a,h" },
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{ "constn", 0x01, "a,X" },
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{ "convert", 0xe4, "c,a,u,r,d,f" },
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{ "cpbyte", 0x2e, "c,a,b" },
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{ "cpbyte", 0x2f, "c,a,i" },
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{ "cpeq", 0x60, "c,a,b" },
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{ "cpeq", 0x61, "c,a,i" },
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{ "cpge", 0x4c, "c,a,b" },
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{ "cpge", 0x4d, "c,a,i" },
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{ "cpgeu", 0x4e, "c,a,b" },
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{ "cpgeu", 0x4f, "c,a,i" },
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{ "cpgt", 0x48, "c,a,b" },
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{ "cpgt", 0x49, "c,a,i" },
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{ "cpgtu", 0x4a, "c,a,b" },
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{ "cpgtu", 0x4b, "c,a,i" },
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{ "cple", 0x44, "c,a,b" },
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{ "cple", 0x45, "c,a,i" },
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{ "cpleu", 0x46, "c,a,b" },
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{ "cpleu", 0x47, "c,a,i" },
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{ "cplt", 0x40, "c,a,b" },
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{ "cplt", 0x41, "c,a,i" },
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{ "cpltu", 0x42, "c,a,b" },
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{ "cpltu", 0x43, "c,a,i" },
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{ "cpneq", 0x62, "c,a,b" },
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{ "cpneq", 0x63, "c,a,i" },
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{ "dadd", 0xf1, "c,a,b" },
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{ "ddiv", 0xf7, "c,a,b" },
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{ "deq", 0xeb, "c,a,b" },
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{ "dge", 0xef, "c,a,b" },
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{ "dgt", 0xed, "c,a,b" },
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{ "div", 0x6a, "c,a,b" },
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{ "div", 0x6b, "c,a,i" },
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{ "div0", 0x68, "c,b" },
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{ "div0", 0x69, "c,i" },
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{ "divide", 0xe1, "c,a,b" },
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{ "dividu", 0xe3, "c,a,b" },
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{ "divl", 0x6c, "c,a,b" },
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{ "divl", 0x6d, "c,a,i" },
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{ "divrem", 0x6e, "c,a,b" },
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{ "divrem", 0x6f, "c,a,i" },
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{ "dmac", 0xd9, "F,C,a,b" },
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{ "dmsm", 0xdb, "c,a,b" },
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{ "dmul", 0xf5, "c,a,b" },
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{ "dsub", 0xf3, "c,a,b" },
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{ "emulate", 0xd7, "v,a,b" },
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{ "exbyte", 0x0a, "c,a,b" },
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{ "exbyte", 0x0b, "c,a,i" },
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{ "exhw", 0x7c, "c,a,b" },
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{ "exhw", 0x7d, "c,a,i" },
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{ "exhws", 0x7e, "c,a" },
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{ "extract", 0x7a, "c,a,b" },
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{ "extract", 0x7b, "c,a,i" },
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{ "fadd", 0xf0, "c,a,b" },
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{ "fdiv", 0xf6, "c,a,b" },
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{ "fdmul", 0xf9, "c,a,b" },
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{ "feq", 0xea, "c,a,b" },
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{ "fge", 0xee, "c,a,b" },
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{ "fgt", 0xec, "c,a,b" },
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{ "fmac", 0xd8, "F,C,a,b" },
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{ "fmsm", 0xda, "c,a,b" },
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{ "fmul", 0xf4, "c,a,b" },
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{ "fsub", 0xf2, "c,a,b" },
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{ "halt", 0x89, "" },
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{ "inbyte", 0x0c, "c,a,b" },
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{ "inbyte", 0x0d, "c,a,i" },
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{ "inhw", 0x78, "c,a,b" },
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{ "inhw", 0x79, "c,a,i" },
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{ "inv", 0x9f, "" },
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{ "iret", 0x88, "" },
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{ "iretinv", 0x8c, "" },
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{ "jmp", 0xa0, "P" },
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{ "jmp", 0xa1, "A" },
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{ "jmpf", 0xa4, "a,P" },
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{ "jmpf", 0xa5, "a,A" },
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{ "jmpfdec", 0xb4, "a,P" },
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{ "jmpfdec", 0xb5, "a,A" },
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{ "jmpfi", 0xc4, "a,b" },
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{ "jmpi", 0xc0, "b" },
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{ "jmpt", 0xac, "a,P" },
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{ "jmpt", 0xad, "a,A" },
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{ "jmpti", 0xcc, "a,b" },
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{ "load", 0x16, "e,n,a,b" },
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{ "load", 0x17, "e,n,a,i" },
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{ "loadl", 0x06, "e,n,a,b" },
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{ "loadl", 0x07, "e,n,a,i" },
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{ "loadm", 0x36, "e,n,a,b" },
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{ "loadm", 0x37, "e,n,a,i" },
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{ "loadset", 0x26, "e,n,a,b" },
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{ "loadset", 0x27, "e,n,a,i" },
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{ "mfacc", 0xe9, "c,d,f" },
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{ "mfsr", 0xc6, "c,s" },
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{ "mftlb", 0xb6, "c,a" },
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{ "mtacc", 0xe8, "a,d,f" },
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{ "mtsr", 0xce, "s,b" },
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{ "mtsrim", 0x04, "s,x" },
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{ "mttlb", 0xbe, "a,b" },
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{ "mul", 0x64, "c,a,b" },
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{ "mul", 0x65, "c,a,i" },
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{ "mull", 0x66, "c,a,b" },
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{ "mull", 0x67, "c,a,i" },
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{ "multiplu", 0xe2, "c,a,b" },
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{ "multiply", 0xe0, "c,a,b" },
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{ "multm", 0xde, "c,a,b" },
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{ "multmu", 0xdf, "c,a,b" },
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{ "mulu", 0x74, "c,a,b" },
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{ "mulu", 0x75, "c,a,i" },
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{ "nand", 0x9a, "c,a,b" },
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{ "nand", 0x9b, "c,a,i" },
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{ "nor", 0x98, "c,a,b" },
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{ "nor", 0x99, "c,a,i" },
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{ "or", 0x92, "c,a,b" },
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{ "or", 0x93, "c,a,i" },
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{ "orn", 0xaa, "c,a,b" },
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{ "orn", 0xab, "c,a,i" },
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/* The description of "setip" in Chapter 8 ("instruction set") of the user's
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manual claims that these are absolute register numbers. But section
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7.2.1 explains that they are not. The latter is correct, so print
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these normally ("lr0", "lr5", etc.). */
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{ "setip", 0x9e, "c,a,b" },
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{ "sll", 0x80, "c,a,b" },
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{ "sll", 0x81, "c,a,i" },
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{ "sqrt", 0xe5, "c,a,f" },
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{ "sra", 0x86, "c,a,b" },
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{ "sra", 0x87, "c,a,i" },
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{ "srl", 0x82, "c,a,b" },
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{ "srl", 0x83, "c,a,i" },
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{ "store", 0x1e, "e,n,a,b" },
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{ "store", 0x1f, "e,n,a,i" },
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{ "storel", 0x0e, "e,n,a,b" },
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{ "storel", 0x0f, "e,n,a,i" },
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{ "storem", 0x3e, "e,n,a,b" },
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{ "storem", 0x3f, "e,n,a,i" },
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{ "sub", 0x24, "c,a,b" },
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{ "sub", 0x25, "c,a,i" },
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{ "subc", 0x2c, "c,a,b" },
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{ "subc", 0x2d, "c,a,i" },
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{ "subcs", 0x28, "c,a,b" },
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{ "subcs", 0x29, "c,a,i" },
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{ "subcu", 0x2a, "c,a,b" },
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{ "subcu", 0x2b, "c,a,i" },
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{ "subr", 0x34, "c,a,b" },
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{ "subr", 0x35, "c,a,i" },
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{ "subrc", 0x3c, "c,a,b" },
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{ "subrc", 0x3d, "c,a,i" },
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{ "subrcs", 0x38, "c,a,b" },
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{ "subrcs", 0x39, "c,a,i" },
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{ "subrcu", 0x3a, "c,a,b" },
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{ "subrcu", 0x3b, "c,a,i" },
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{ "subrs", 0x30, "c,a,b" },
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{ "subrs", 0x31, "c,a,i" },
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{ "subru", 0x32, "c,a,b" },
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{ "subru", 0x33, "c,a,i" },
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{ "subs", 0x20, "c,a,b" },
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{ "subs", 0x21, "c,a,i" },
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{ "subu", 0x22, "c,a,b" },
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{ "subu", 0x23, "c,a,i" },
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{ "xnor", 0x96, "c,a,b" },
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{ "xnor", 0x97, "c,a,i" },
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{ "xor", 0x94, "c,a,b" },
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{ "xor", 0x95, "c,a,i" }
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};
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#define NUM_OPCODES ((sizeof am29k_opcodes) / (sizeof am29k_opcodes[0]))
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