101 lines
5 KiB
C
101 lines
5 KiB
C
/* ARM assembler/disassembler support.
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Copyright 2004 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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GDB and GAS are free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 1, or (at
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your option) any later version.
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GDB and GAS are distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GDB or GAS; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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/* The following bitmasks control CPU extensions: */
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#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
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#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
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#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
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#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
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#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
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#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
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#define ARM_EXT_V4T 0x00000040 /* Thumb. */
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#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
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#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
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#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
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#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
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#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
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#define ARM_EXT_V6 0x00001000 /* ARM V6. */
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#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
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#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
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#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
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/* Co-processor space extensions. */
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#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */
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#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */
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#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */
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/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
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defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
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ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
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three more to cover cores prior to ARM6. Finally, there are cores which
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implement further extensions in the co-processor space. */
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#define ARM_ARCH_V1 ARM_EXT_V1
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#define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2)
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#define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S)
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#define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3)
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#define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M)
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#define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4)
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#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4)
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#define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T)
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#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T)
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#define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5)
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#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
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#define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
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#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
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#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP)
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#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E)
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#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J)
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#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6)
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#define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K)
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#define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z)
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#define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
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#define ARM_ARCH_V6T2 (ARM_ARCH_V6 | ARM_EXT_V6T2)
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#define ARM_ARCH_V6KT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K)
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#define ARM_ARCH_V6ZT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6Z)
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#define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
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/* Processors with specific extensions in the co-processor space. */
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#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE)
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#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
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#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */
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#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */
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#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */
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#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */
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#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */
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#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */
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#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */
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#define FPU_NONE 0
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#define FPU_ARCH_FPE FPU_FPA_EXT_V1
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#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2)
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#define FPU_ARCH_VFP FPU_VFP_EXT_NONE
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#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
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#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
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#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
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#define FPU_ARCH_MAVERICK FPU_MAVERICK
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/* Some useful combinations: */
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#define ARM_ANY 0x0000ffff /* Any basic core. */
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#define ARM_ALL 0x00ffffff /* Any core + co-processor */
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#define CPROC_ANY 0x00ff0000 /* Any co-processor */
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#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */
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