589 lines
19 KiB
C
589 lines
19 KiB
C
/* Target machine description for generic Motorola 88000, for GDB.
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Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1994, 1996, 1998,
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1999, 2000
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include "doublest.h"
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#include "regcache.h"
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/* g++ support is not yet included. */
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/* We cache information about saved registers in the frame structure,
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to save us from having to re-scan function prologues every time
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a register in a non-current frame is accessed. */
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#define EXTRA_FRAME_INFO \
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struct frame_saved_regs *fsr; \
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CORE_ADDR locals_pointer; \
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CORE_ADDR args_pointer;
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/* Zero the frame_saved_regs pointer when the frame is initialized,
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so that FRAME_FIND_SAVED_REGS () will know to allocate and
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initialize a frame_saved_regs struct the first time it is called.
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Set the arg_pointer to -1, which is not valid; 0 and other values
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indicate real, cached values. */
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#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
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init_extra_frame_info (fromleaf, fi)
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extern void init_extra_frame_info ();
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/* Offset from address of function to start of its code.
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Zero on most machines. */
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#define FUNCTION_START_OFFSET 0
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/* Advance PC across any function entry prologue instructions
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to reach some "real" code. */
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extern CORE_ADDR m88k_skip_prologue (CORE_ADDR);
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#define SKIP_PROLOGUE(frompc) (m88k_skip_prologue (frompc))
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/* The m88k kernel aligns all instructions on 4-byte boundaries. The
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kernel also uses the least significant two bits for its own hocus
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pocus. When gdb receives an address from the kernel, it needs to
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preserve those right-most two bits, but gdb also needs to be careful
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to realize that those two bits are not really a part of the address
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of an instruction. Shrug. */
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extern CORE_ADDR m88k_addr_bits_remove (CORE_ADDR);
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#define ADDR_BITS_REMOVE(addr) m88k_addr_bits_remove (addr)
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/* Immediately after a function call, return the saved pc.
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Can't always go through the frames for this because on some machines
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the new frame is not set up until the new function executes
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some instructions. */
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#define SAVED_PC_AFTER_CALL(frame) \
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(ADDR_BITS_REMOVE (read_register (SRP_REGNUM)))
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/* Stack grows downward. */
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#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
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/* Sequence of bytes for breakpoint instruction. */
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/* instruction 0xF000D1FF is 'tb0 0,r0,511'
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If Bit bit 0 of r0 is clear (always true),
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initiate exception processing (trap).
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*/
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#define BREAKPOINT {0xF0, 0x00, 0xD1, 0xFF}
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/* Amount PC must be decremented by after a breakpoint.
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This is often the number of bytes in BREAKPOINT
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but not always. */
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#define DECR_PC_AFTER_BREAK 0
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/* Say how long (ordinary) registers are. This is a piece of bogosity
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used in push_word and a few other places; REGISTER_RAW_SIZE is the
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real way to know how big a register is. */
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#define REGISTER_SIZE 4
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/* Number of machine registers */
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#define GP_REGS (38)
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#define FP_REGS (32)
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#define NUM_REGS (GP_REGS + FP_REGS)
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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#define REGISTER_NAMES {\
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"r0",\
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"r1",\
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"r2",\
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"r3",\
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"r4",\
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"r5",\
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"r6",\
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"r7",\
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"r8",\
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"r9",\
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"r10",\
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"r11",\
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"r12",\
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"r13",\
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"r14",\
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"r15",\
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"r16",\
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"r17",\
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"r18",\
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"r19",\
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"r20",\
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"r21",\
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"r22",\
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"r23",\
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"r24",\
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"r25",\
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"r26",\
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"r27",\
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"r28",\
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"r29",\
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"r30",\
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"r31",\
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"psr",\
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"fpsr",\
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"fpcr",\
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"sxip",\
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"snip",\
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"sfip",\
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"x0",\
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"x1",\
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"x2",\
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"x3",\
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"x4",\
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"x5",\
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"x6",\
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"x7",\
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"x8",\
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"x9",\
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"x10",\
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"x11",\
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"x12",\
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"x13",\
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"x14",\
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"x15",\
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"x16",\
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"x17",\
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"x18",\
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"x19",\
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"x20",\
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"x21",\
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"x22",\
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"x23",\
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"x24",\
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"x25",\
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"x26",\
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"x27",\
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"x28",\
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"x29",\
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"x30",\
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"x31",\
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"vbr",\
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"dmt0",\
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"dmd0",\
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"dma0",\
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"dmt1",\
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"dmd1",\
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"dma1",\
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"dmt2",\
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"dmd2",\
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"dma2",\
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"sr0",\
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"sr1",\
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"sr2",\
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"sr3",\
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"fpecr",\
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"fphs1",\
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"fpls1",\
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"fphs2",\
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"fpls2",\
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"fppt",\
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"fprh",\
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"fprl",\
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"fpit",\
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"fpsr",\
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"fpcr",\
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}
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/* Register numbers of various important registers.
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Note that some of these values are "real" register numbers,
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and correspond to the general registers of the machine,
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and some are "phony" register numbers which are too large
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to be actual register numbers as far as the user is concerned
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but do serve to get the desired values when passed to read_register. */
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#define R0_REGNUM 0 /* Contains the constant zero */
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#define SRP_REGNUM 1 /* Contains subroutine return pointer */
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#define RV_REGNUM 2 /* Contains simple return values */
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#define SRA_REGNUM 12 /* Contains address of struct return values */
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#define SP_REGNUM 31 /* Contains address of top of stack */
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/* Instruction pointer notes...
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On the m88100:
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* cr04 = sxip. On exception, contains the excepting pc (probably).
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On rte, is ignored.
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* cr05 = snip. On exception, contains the NPC (next pc). On rte,
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pc is loaded from here.
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* cr06 = sfip. On exception, contains the NNPC (next next pc). On
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rte, the NPC is loaded from here.
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* lower two bits of each are flag bits. Bit 1 is V means address
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is valid. If address is not valid, bit 0 is ignored. Otherwise,
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bit 0 is E and asks for an exception to be taken if this
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instruction is executed.
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On the m88110:
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* cr04 = exip. On exception, contains the address of the excepting
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pc (always). On rte, pc is loaded from here. Bit 0, aka the D
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bit, is a flag saying that the offending instruction was in a
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branch delay slot. If set, then cr05 contains the NPC.
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* cr05 = enip. On exception, if the instruction pointed to by cr04
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was in a delay slot as indicated by the bit 0 of cr04, aka the D
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bit, the cr05 contains the NPC. Otherwise ignored.
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* cr06 is invalid */
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/* Note that the Harris Unix kernels emulate the m88100's behavior on
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the m88110. */
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#define SXIP_REGNUM 35 /* On m88100, Contains Shadow Execute
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Instruction Pointer. */
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#define SNIP_REGNUM 36 /* On m88100, Contains Shadow Next
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Instruction Pointer. */
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#define SFIP_REGNUM 37 /* On m88100, Contains Shadow Fetched
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Intruction pointer. */
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#define EXIP_REGNUM 35 /* On m88110, Contains Exception
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Executing Instruction Pointer. */
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#define ENIP_REGNUM 36 /* On m88110, Contains the Exception
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Next Instruction Pointer. */
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#define PC_REGNUM SXIP_REGNUM /* Program Counter */
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#define NPC_REGNUM SNIP_REGNUM /* Next Program Counter */
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#define NNPC_REGNUM SFIP_REGNUM /* Next Next Program Counter */
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#define PSR_REGNUM 32 /* Processor Status Register */
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#define FPSR_REGNUM 33 /* Floating Point Status Register */
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#define FPCR_REGNUM 34 /* Floating Point Control Register */
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#define XFP_REGNUM 38 /* First Extended Float Register */
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#define X0_REGNUM XFP_REGNUM /* Which also contains the constant zero */
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/* This is rather a confusing lie. Our m88k port using a stack pointer value
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for the frame address. Hence, the frame address and the frame pointer are
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only indirectly related. The value of this macro is the register number
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fetched by the machine "independent" portions of gdb when they want to know
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about a frame address. Thus, we lie here and claim that FP_REGNUM is
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SP_REGNUM. */
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#define FP_REGNUM SP_REGNUM /* Reg fetched to locate frame when pgm stops */
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#define ACTUAL_FP_REGNUM 30
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/* PSR status bit definitions. */
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#define PSR_MODE 0x80000000
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#define PSR_BYTE_ORDER 0x40000000
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#define PSR_SERIAL_MODE 0x20000000
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#define PSR_CARRY 0x10000000
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#define PSR_SFU_DISABLE 0x000003f0
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#define PSR_SFU1_DISABLE 0x00000008
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#define PSR_MXM 0x00000004
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#define PSR_IND 0x00000002
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#define PSR_SFRZ 0x00000001
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/* The following two comments come from the days prior to the m88110
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port. The m88110 handles the instruction pointers differently. I
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do not know what any m88110 kernels do as the m88110 port I'm
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working with is for an embedded system. rich@cygnus.com
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13-sept-93. */
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/* BCS requires that the SXIP_REGNUM (or PC_REGNUM) contain the
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address of the next instr to be executed when a breakpoint occurs.
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Because the kernel gets the next instr (SNIP_REGNUM), the instr in
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SNIP needs to be put back into SFIP, and the instr in SXIP should
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be shifted to SNIP */
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/* Are you sitting down? It turns out that the 88K BCS (binary
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compatibility standard) folks originally felt that the debugger
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should be responsible for backing up the IPs, not the kernel (as is
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usually done). Well, they have reversed their decision, and in
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future releases our kernel will be handling the backing up of the
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IPs. So, eventually, we won't need to do the SHIFT_INST_REGS
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stuff. But, for now, since there are 88K systems out there that do
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need the debugger to do the IP shifting, and since there will be
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systems where the kernel does the shifting, the code is a little
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more complex than perhaps it needs to be (we still go inside
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SHIFT_INST_REGS, and if the shifting hasn't occurred then gdb goes
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ahead and shifts). */
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extern int target_is_m88110;
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#define SHIFT_INST_REGS() \
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if (!target_is_m88110) \
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{ \
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CORE_ADDR pc = read_register (PC_REGNUM); \
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CORE_ADDR npc = read_register (NPC_REGNUM); \
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if (pc != npc) \
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{ \
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write_register (NNPC_REGNUM, npc); \
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write_register (NPC_REGNUM, pc); \
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} \
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}
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/* Storing the following registers is a no-op. */
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#define CANNOT_STORE_REGISTER(regno) (((regno) == R0_REGNUM) \
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|| ((regno) == X0_REGNUM))
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/* Number of bytes of storage in the actual machine representation
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for register N. On the m88k, the general purpose registers are 4
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bytes and the 88110 extended registers are 10 bytes. */
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#define REGISTER_RAW_SIZE(N) ((N) < XFP_REGNUM ? 4 : 10)
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_BYTES ((GP_REGS * REGISTER_RAW_SIZE(0)) \
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+ (FP_REGS * REGISTER_RAW_SIZE(XFP_REGNUM)))
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/* Index within `registers' of the first byte of the space for
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register N. */
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#define REGISTER_BYTE(N) (((N) * REGISTER_RAW_SIZE(0)) \
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+ ((N) >= XFP_REGNUM \
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? (((N) - XFP_REGNUM) \
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* REGISTER_RAW_SIZE(XFP_REGNUM)) \
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: 0))
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/* Number of bytes of storage in the program's representation for
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register N. On the m88k, all registers are 4 bytes excepting the
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m88110 extended registers which are 8 byte doubles. */
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#define REGISTER_VIRTUAL_SIZE(N) ((N) < XFP_REGNUM ? 4 : 8)
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/* Largest value REGISTER_RAW_SIZE can have. */
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#define MAX_REGISTER_RAW_SIZE (REGISTER_RAW_SIZE(XFP_REGNUM))
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/* Largest value REGISTER_VIRTUAL_SIZE can have.
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Are FPS1, FPS2, FPR "virtual" regisers? */
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#define MAX_REGISTER_VIRTUAL_SIZE (REGISTER_RAW_SIZE(XFP_REGNUM))
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/* Return the GDB type object for the "standard" data type
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of data in register N. */
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struct type *m88k_register_type (int regnum);
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#define REGISTER_VIRTUAL_TYPE(N) m88k_register_type (N)
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/* The 88k call/return conventions call for "small" values to be returned
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into consecutive registers starting from r2. */
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#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
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memcpy ((VALBUF), &(((char *)REGBUF)[REGISTER_BYTE(RV_REGNUM)]), TYPE_LENGTH (TYPE))
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) (*(int *)(REGBUF))
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/* Write into appropriate registers a function return value
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of type TYPE, given in virtual format. */
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#define STORE_RETURN_VALUE(TYPE,VALBUF) \
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write_register_bytes (2*REGISTER_RAW_SIZE(0), (VALBUF), TYPE_LENGTH (TYPE))
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/* In COFF, if PCC says a parameter is a short or a char, do not
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change it to int (it seems the convention is to change it). */
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#define BELIEVE_PCC_PROMOTION 1
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/* Describe the pointer in each stack frame to the previous stack frame
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(its caller). */
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/* FRAME_CHAIN takes a frame's nominal address
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and produces the frame's chain-pointer.
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However, if FRAME_CHAIN_VALID returns zero,
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it means the given frame is the outermost one and has no caller. */
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extern CORE_ADDR frame_chain ();
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extern int frame_chain_valid ();
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extern int frameless_function_invocation ();
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#define FRAME_CHAIN(thisframe) \
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frame_chain (thisframe)
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#define FRAMELESS_FUNCTION_INVOCATION(frame) \
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(frameless_function_invocation (frame))
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/* Define other aspects of the stack frame. */
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#define FRAME_SAVED_PC(FRAME) \
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frame_saved_pc (FRAME)
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extern CORE_ADDR frame_saved_pc ();
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#define FRAME_ARGS_ADDRESS(fi) \
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frame_args_address (fi)
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extern CORE_ADDR frame_args_address ();
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#define FRAME_LOCALS_ADDRESS(fi) \
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frame_locals_address (fi)
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extern CORE_ADDR frame_locals_address ();
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/* Return number of args passed to a frame.
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Can return -1, meaning no way to tell. */
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#define FRAME_NUM_ARGS(fi) (-1)
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/* Return number of bytes at start of arglist that are not really args. */
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#define FRAME_ARGS_SKIP 0
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/* Put here the code to store, into a struct frame_saved_regs,
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the addresses of the saved registers of frame described by FRAME_INFO.
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This includes special registers such as pc and fp saved in special
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ways in the stack frame. sp is even more special:
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the address we return for it IS the sp for the next frame. */
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/* On the 88k, parameter registers get stored into the so called "homing"
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area. This *always* happens when you compiled with GCC and use -g.
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Also, (with GCC and -g) the saving of the parameter register values
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always happens right within the function prologue code, so these register
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values can generally be relied upon to be already copied into their
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respective homing slots by the time you will normally try to look at
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them (we hope).
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Note that homing area stack slots are always at *positive* offsets from
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the frame pointer. Thus, the homing area stack slots for the parameter
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registers (passed values) for a given function are actually part of the
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frame area of the caller. This is unusual, but it should not present
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any special problems for GDB.
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Note also that on the 88k, we are only interested in finding the
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registers that might have been saved in memory. This is a subset of
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the whole set of registers because the standard calling sequence allows
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the called routine to clobber many registers.
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We could manage to locate values for all of the so called "preserved"
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registers (some of which may get saved within any particular frame) but
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that would require decoding all of the tdesc information. That would be
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nice information for GDB to have, but it is not strictly manditory if we
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can live without the ability to look at values within (or backup to)
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previous frames.
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*/
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struct frame_saved_regs;
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struct frame_info;
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void frame_find_saved_regs (struct frame_info *fi,
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struct frame_saved_regs *fsr);
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#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
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frame_find_saved_regs (frame_info, &frame_saved_regs)
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#define POP_FRAME pop_frame ()
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extern void pop_frame ();
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/* Call function stuff contributed by Kevin Buettner of Motorola. */
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#define CALL_DUMMY_LOCATION AFTER_TEXT_END
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extern void m88k_push_dummy_frame ();
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#define PUSH_DUMMY_FRAME m88k_push_dummy_frame()
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#define CALL_DUMMY { \
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0x67ff00c0, /* 0: subu #sp,#sp,0xc0 */ \
|
||
0x243f0004, /* 4: st #r1,#sp,0x4 */ \
|
||
0x245f0008, /* 8: st #r2,#sp,0x8 */ \
|
||
0x247f000c, /* c: st #r3,#sp,0xc */ \
|
||
0x249f0010, /* 10: st #r4,#sp,0x10 */ \
|
||
0x24bf0014, /* 14: st #r5,#sp,0x14 */ \
|
||
0x24df0018, /* 18: st #r6,#sp,0x18 */ \
|
||
0x24ff001c, /* 1c: st #r7,#sp,0x1c */ \
|
||
0x251f0020, /* 20: st #r8,#sp,0x20 */ \
|
||
0x253f0024, /* 24: st #r9,#sp,0x24 */ \
|
||
0x255f0028, /* 28: st #r10,#sp,0x28 */ \
|
||
0x257f002c, /* 2c: st #r11,#sp,0x2c */ \
|
||
0x259f0030, /* 30: st #r12,#sp,0x30 */ \
|
||
0x25bf0034, /* 34: st #r13,#sp,0x34 */ \
|
||
0x25df0038, /* 38: st #r14,#sp,0x38 */ \
|
||
0x25ff003c, /* 3c: st #r15,#sp,0x3c */ \
|
||
0x261f0040, /* 40: st #r16,#sp,0x40 */ \
|
||
0x263f0044, /* 44: st #r17,#sp,0x44 */ \
|
||
0x265f0048, /* 48: st #r18,#sp,0x48 */ \
|
||
0x267f004c, /* 4c: st #r19,#sp,0x4c */ \
|
||
0x269f0050, /* 50: st #r20,#sp,0x50 */ \
|
||
0x26bf0054, /* 54: st #r21,#sp,0x54 */ \
|
||
0x26df0058, /* 58: st #r22,#sp,0x58 */ \
|
||
0x26ff005c, /* 5c: st #r23,#sp,0x5c */ \
|
||
0x271f0060, /* 60: st #r24,#sp,0x60 */ \
|
||
0x273f0064, /* 64: st #r25,#sp,0x64 */ \
|
||
0x275f0068, /* 68: st #r26,#sp,0x68 */ \
|
||
0x277f006c, /* 6c: st #r27,#sp,0x6c */ \
|
||
0x279f0070, /* 70: st #r28,#sp,0x70 */ \
|
||
0x27bf0074, /* 74: st #r29,#sp,0x74 */ \
|
||
0x27df0078, /* 78: st #r30,#sp,0x78 */ \
|
||
0x63df0000, /* 7c: addu #r30,#sp,0x0 */ \
|
||
0x145f0000, /* 80: ld #r2,#sp,0x0 */ \
|
||
0x147f0004, /* 84: ld #r3,#sp,0x4 */ \
|
||
0x149f0008, /* 88: ld #r4,#sp,0x8 */ \
|
||
0x14bf000c, /* 8c: ld #r5,#sp,0xc */ \
|
||
0x14df0010, /* 90: ld #r6,#sp,0x10 */ \
|
||
0x14ff0014, /* 94: ld #r7,#sp,0x14 */ \
|
||
0x151f0018, /* 98: ld #r8,#sp,0x18 */ \
|
||
0x153f001c, /* 9c: ld #r9,#sp,0x1c */ \
|
||
0x5c200000, /* a0: or.u #r1,#r0,0x0 */ \
|
||
0x58210000, /* a4: or #r1,#r1,0x0 */ \
|
||
0xf400c801, /* a8: jsr #r1 */ \
|
||
0xf000d1ff /* ac: tb0 0x0,#r0,0x1ff */ \
|
||
}
|
||
|
||
#define CALL_DUMMY_START_OFFSET 0x80
|
||
#define CALL_DUMMY_LENGTH 0xb0
|
||
|
||
/* FIXME: byteswapping. */
|
||
#define FIX_CALL_DUMMY(dummy, pc, fun, nargs, args, type, gcc_p) \
|
||
{ \
|
||
*(unsigned long *)((char *) (dummy) + 0xa0) |= \
|
||
(((unsigned long) (fun)) >> 16); \
|
||
*(unsigned long *)((char *) (dummy) + 0xa4) |= \
|
||
(((unsigned long) (fun)) & 0xffff); \
|
||
}
|
||
|
||
/* Stack must be aligned on 64-bit boundaries when synthesizing
|
||
function calls. */
|
||
|
||
#define STACK_ALIGN(addr) (((addr) + 7) & -8)
|
||
|
||
#define STORE_STRUCT_RETURN(addr, sp) \
|
||
write_register (SRA_REGNUM, (addr))
|
||
|
||
#define NEED_TEXT_START_END 1
|
||
|
||
/* According to the MC88100 RISC Microprocessor User's Manual, section
|
||
6.4.3.1.2:
|
||
|
||
... can be made to return to a particular instruction by placing a
|
||
valid instruction address in the SNIP and the next sequential
|
||
instruction address in the SFIP (with V bits set and E bits clear).
|
||
The rte resumes execution at the instruction pointed to by the
|
||
SNIP, then the SFIP.
|
||
|
||
The E bit is the least significant bit (bit 0). The V (valid) bit is
|
||
bit 1. This is why we logical or 2 into the values we are writing
|
||
below. It turns out that SXIP plays no role when returning from an
|
||
exception so nothing special has to be done with it. We could even
|
||
(presumably) give it a totally bogus value.
|
||
|
||
-- Kevin Buettner
|
||
*/
|
||
|
||
#define TARGET_WRITE_PC(val, pid) { \
|
||
write_register_pid(SXIP_REGNUM, (long) val, pid); \
|
||
write_register_pid(SNIP_REGNUM, (long) val | 2, pid); \
|
||
write_register_pid(SFIP_REGNUM, ((long) val | 2) + 4, pid); \
|
||
}
|