6bb95a0ff8
* cgen-ibld.in (cgen_put_insn_int_value): New function. (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. * cgen-dis.in (read_insn): New static function. (print_insn): Use read_insn to read the insn into the buffer and set up for disassembly. (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is in the buffer. * fr30-asm.c: Regenerated. * fr30-desc.c: Regenerated. * fr30-desc.h Regenerated. * fr30-dis.c: Regenerated. * fr30-ibld.c: Regenerated. * fr30-opc.c: Regenerated. * fr30-opc.h Regenerated. * m32r-asm.c: Regenerated. * m32r-desc.c: Regenerated. * m32r-desc.h Regenerated. * m32r-dis.c: Regenerated. * m32r-ibld.c: Regenerated. * m32r-opc.c: Regenerated.
589 lines
18 KiB
C
589 lines
18 KiB
C
/* Assembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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- the resultant file is machine generated, cgen-asm.in isn't
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Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <ctype.h>
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#include <stdio.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "fr30-desc.h"
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#include "fr30-opc.h"
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#include "opintl.h"
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#undef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#undef max
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#define max(a,b) ((a) > (b) ? (a) : (b))
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static const char * parse_insn_normal
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PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
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/* -- assembler routines inserted here */
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/* -- asm.c */
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/* Handle register lists for LDMx and STMx */
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static int
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parse_register_number (strp)
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const char **strp;
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{
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int regno;
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if (**strp < '0' || **strp > '9')
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return -1; /* error */
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regno = **strp - '0';
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++*strp;
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if (**strp >= '0' && **strp <= '9')
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{
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regno = regno * 10 + (**strp - '0');
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++*strp;
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}
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return regno;
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}
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static const char *
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parse_register_list (cd, strp, opindex, valuep, high_low, load_store)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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int high_low; /* 0 == high, 1 == low */
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int load_store; /* 0 == load, 1 == store */
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{
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int regno;
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*valuep = 0;
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while (**strp && **strp != ')')
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{
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if (**strp != 'R' && **strp != 'r')
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break;
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++*strp;
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regno = parse_register_number (strp);
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if (regno == -1)
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return "Register number is not valid";
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if (regno > 7 && !high_low)
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return "Register must be between r0 and r7";
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if (regno < 8 && high_low)
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return "Register must be between r8 and r15";
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if (high_low)
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regno -= 8;
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if (load_store) /* mask is reversed for store */
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*valuep |= 0x80 >> regno;
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else
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*valuep |= 1 << regno;
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if (**strp == ',')
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{
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if (*(*strp + 1) == ')')
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break;
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++*strp;
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}
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}
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if (!*strp || **strp != ')')
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return "Register list is not valid";
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return NULL;
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}
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static const char *
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parse_low_register_list_ld (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 0/*load*/);
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}
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static const char *
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parse_hi_register_list_ld (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 0/*load*/);
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}
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static const char *
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parse_low_register_list_st (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 1/*store*/);
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}
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static const char *
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parse_hi_register_list_st (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 1/*store*/);
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}
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/* -- */
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/* Main entry point for operand parsing.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers.
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*/
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const char *
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fr30_cgen_parse_operand (cd, opindex, strp, fields)
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CGEN_CPU_DESC cd;
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int opindex;
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const char ** strp;
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CGEN_FIELDS * fields;
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{
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const char * errmsg = NULL;
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/* Used by scalar operands that still need to be parsed. */
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long junk;
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switch (opindex)
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{
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case FR30_OPERAND_CRI :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRi);
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break;
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case FR30_OPERAND_CRJ :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRj);
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break;
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case FR30_OPERAND_R13 :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r13, & junk);
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break;
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case FR30_OPERAND_R14 :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r14, & junk);
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break;
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case FR30_OPERAND_R15 :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r15, & junk);
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break;
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case FR30_OPERAND_RI :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ri);
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break;
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case FR30_OPERAND_RIC :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ric);
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break;
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case FR30_OPERAND_RJ :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Rj);
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break;
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case FR30_OPERAND_RJC :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Rjc);
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break;
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case FR30_OPERAND_RS1 :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_dr_names, & fields->f_Rs1);
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break;
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case FR30_OPERAND_RS2 :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_dr_names, & fields->f_Rs2);
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break;
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case FR30_OPERAND_CC :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_CC, &fields->f_cc);
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break;
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case FR30_OPERAND_CCC :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_CCC, &fields->f_ccc);
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break;
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case FR30_OPERAND_DIR10 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR10, &fields->f_dir10);
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break;
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case FR30_OPERAND_DIR8 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR8, &fields->f_dir8);
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break;
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case FR30_OPERAND_DIR9 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR9, &fields->f_dir9);
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break;
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case FR30_OPERAND_DISP10 :
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errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP10, &fields->f_disp10);
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break;
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case FR30_OPERAND_DISP8 :
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errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP8, &fields->f_disp8);
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break;
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case FR30_OPERAND_DISP9 :
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errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP9, &fields->f_disp9);
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break;
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case FR30_OPERAND_I20 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I20, &fields->f_i20);
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break;
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case FR30_OPERAND_I32 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I32, &fields->f_i32);
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break;
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case FR30_OPERAND_I8 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I8, &fields->f_i8);
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break;
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case FR30_OPERAND_LABEL12 :
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{
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bfd_vma value;
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errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL12, 0, NULL, & value);
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fields->f_rel12 = value;
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}
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break;
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case FR30_OPERAND_LABEL9 :
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{
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bfd_vma value;
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errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL9, 0, NULL, & value);
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fields->f_rel9 = value;
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}
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break;
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case FR30_OPERAND_M4 :
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errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_M4, &fields->f_m4);
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break;
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case FR30_OPERAND_PS :
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errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_ps, & junk);
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break;
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case FR30_OPERAND_REGLIST_HI_LD :
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errmsg = parse_hi_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_HI_LD, &fields->f_reglist_hi_ld);
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break;
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case FR30_OPERAND_REGLIST_HI_ST :
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errmsg = parse_hi_register_list_st (cd, strp, FR30_OPERAND_REGLIST_HI_ST, &fields->f_reglist_hi_st);
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break;
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case FR30_OPERAND_REGLIST_LOW_LD :
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errmsg = parse_low_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_LOW_LD, &fields->f_reglist_low_ld);
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break;
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case FR30_OPERAND_REGLIST_LOW_ST :
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errmsg = parse_low_register_list_st (cd, strp, FR30_OPERAND_REGLIST_LOW_ST, &fields->f_reglist_low_st);
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break;
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case FR30_OPERAND_S10 :
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errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_S10, &fields->f_s10);
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break;
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case FR30_OPERAND_U10 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U10, &fields->f_u10);
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break;
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case FR30_OPERAND_U4 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U4, &fields->f_u4);
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break;
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case FR30_OPERAND_U4C :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U4C, &fields->f_u4c);
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break;
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case FR30_OPERAND_U8 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U8, &fields->f_u8);
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break;
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case FR30_OPERAND_UDISP6 :
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errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_UDISP6, &fields->f_udisp6);
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
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abort ();
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}
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return errmsg;
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}
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cgen_parse_fn * const fr30_cgen_parse_handlers[] =
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{
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parse_insn_normal,
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};
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void
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fr30_cgen_init_asm (cd)
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CGEN_CPU_DESC cd;
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{
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fr30_cgen_init_opcode_table (cd);
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fr30_cgen_init_ibld_table (cd);
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cd->parse_handlers = & fr30_cgen_parse_handlers[0];
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cd->parse_operand = fr30_cgen_parse_operand;
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}
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/* Default insn parser.
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The syntax string is scanned and operands are parsed and stored in FIELDS.
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Relocs are queued as we go via other callbacks.
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??? Note that this is currently an all-or-nothing parser. If we fail to
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parse the instruction, we return 0 and the caller will start over from
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the beginning. Backtracking will be necessary in parsing subexpressions,
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but that can be handled there. Not handling backtracking here may get
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expensive in the case of the m68k. Deal with later.
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Returns NULL for success, an error message for failure.
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*/
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static const char *
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parse_insn_normal (cd, insn, strp, fields)
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CGEN_CPU_DESC cd;
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const CGEN_INSN *insn;
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const char **strp;
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CGEN_FIELDS *fields;
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{
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/* ??? Runtime added insns not handled yet. */
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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const char *str = *strp;
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const char *errmsg;
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const char *p;
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const unsigned char * syn;
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#ifdef CGEN_MNEMONIC_OPERANDS
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/* FIXME: wip */
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int past_opcode_p;
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#endif
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/* For now we assume the mnemonic is first (there are no leading operands).
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We can parse it without needing to set up operand parsing.
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GAS's input scrubber will ensure mnemonics are lowercase, but we may
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not be called from GAS. */
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p = CGEN_INSN_MNEMONIC (insn);
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while (*p && tolower (*p) == tolower (*str))
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++p, ++str;
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if (* p)
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return _("unrecognized instruction");
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#ifndef CGEN_MNEMONIC_OPERANDS
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if (* str && !isspace (* str))
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return _("unrecognized instruction");
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#endif
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CGEN_INIT_PARSE (cd);
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cgen_init_parse_operand (cd);
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#ifdef CGEN_MNEMONIC_OPERANDS
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past_opcode_p = 0;
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#endif
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/* We don't check for (*str != '\0') here because we want to parse
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any trailing fake arguments in the syntax string. */
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syn = CGEN_SYNTAX_STRING (syntax);
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/* Mnemonics come first for now, ensure valid string. */
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if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
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abort ();
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++syn;
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while (* syn != 0)
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{
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/* Non operand chars must match exactly. */
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if (CGEN_SYNTAX_CHAR_P (* syn))
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{
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/* FIXME: While we allow for non-GAS callers above, we assume the
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first char after the mnemonic part is a space. */
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/* FIXME: We also take inappropriate advantage of the fact that
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GAS's input scrubber will remove extraneous blanks. */
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if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
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{
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#ifdef CGEN_MNEMONIC_OPERANDS
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if (* syn == ' ')
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past_opcode_p = 1;
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#endif
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++ syn;
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++ str;
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}
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else
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{
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/* Syntax char didn't match. Can't be this insn. */
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static char msg [80];
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/* xgettext:c-format */
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sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
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*syn, *str);
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return msg;
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}
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continue;
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}
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/* We have an operand of some sort. */
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errmsg = fr30_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
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&str, fields);
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if (errmsg)
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return errmsg;
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/* Done with this operand, continue with next one. */
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++ syn;
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}
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/* If we're at the end of the syntax string, we're done. */
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if (* syn == '\0')
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{
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/* FIXME: For the moment we assume a valid `str' can only contain
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blanks now. IE: We needn't try again with a longer version of
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the insn and it is assumed that longer versions of insns appear
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before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
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while (isspace (* str))
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++ str;
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if (* str != '\0')
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return _("junk at end of line"); /* FIXME: would like to include `str' */
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return NULL;
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}
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/* We couldn't parse it. */
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return _("unrecognized instruction");
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}
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/* Main entry point.
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This routine is called for each instruction to be assembled.
|
||
STR points to the insn to be assembled.
|
||
We assume all necessary tables have been initialized.
|
||
The assembled instruction, less any fixups, is stored in BUF.
|
||
Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
|
||
still needs to be converted to target byte order, otherwise BUF is an array
|
||
of bytes in target byte order.
|
||
The result is a pointer to the insn's entry in the opcode table,
|
||
or NULL if an error occured (an error message will have already been
|
||
printed).
|
||
|
||
Note that when processing (non-alias) macro-insns,
|
||
this function recurses.
|
||
|
||
??? It's possible to make this cpu-independent.
|
||
One would have to deal with a few minor things.
|
||
At this point in time doing so would be more of a curiosity than useful
|
||
[for example this file isn't _that_ big], but keeping the possibility in
|
||
mind helps keep the design clean. */
|
||
|
||
const CGEN_INSN *
|
||
fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg)
|
||
CGEN_CPU_DESC cd;
|
||
const char *str;
|
||
CGEN_FIELDS *fields;
|
||
CGEN_INSN_BYTES_PTR buf;
|
||
char **errmsg;
|
||
{
|
||
const char *start;
|
||
CGEN_INSN_LIST *ilist;
|
||
const char *tmp_errmsg = NULL;
|
||
|
||
/* Skip leading white space. */
|
||
while (isspace (* str))
|
||
++ str;
|
||
|
||
/* The instructions are stored in hashed lists.
|
||
Get the first in the list. */
|
||
ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
|
||
|
||
/* Keep looking until we find a match. */
|
||
|
||
start = str;
|
||
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
|
||
{
|
||
const CGEN_INSN *insn = ilist->insn;
|
||
|
||
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
|
||
/* not usually needed as unsupported opcodes shouldn't be in the hash lists */
|
||
/* Is this insn supported by the selected cpu? */
|
||
if (! fr30_cgen_insn_supported (cd, insn))
|
||
continue;
|
||
#endif
|
||
|
||
/* If the RELAX attribute is set, this is an insn that shouldn't be
|
||
chosen immediately. Instead, it is used during assembler/linker
|
||
relaxation if possible. */
|
||
if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
|
||
continue;
|
||
|
||
str = start;
|
||
|
||
/* Allow parse/insert handlers to obtain length of insn. */
|
||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||
|
||
tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
|
||
if (tmp_errmsg != NULL)
|
||
continue;
|
||
|
||
/* ??? 0 is passed for `pc' */
|
||
tmp_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
|
||
(bfd_vma) 0);
|
||
if (tmp_errmsg != NULL)
|
||
continue;
|
||
|
||
/* It is up to the caller to actually output the insn and any
|
||
queued relocs. */
|
||
return insn;
|
||
}
|
||
|
||
/* Make sure we leave this with something at this point. */
|
||
if (tmp_errmsg == NULL)
|
||
tmp_errmsg = "unknown mnemonic";
|
||
|
||
{
|
||
static char errbuf[150];
|
||
|
||
#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||
/* if verbose error messages, use errmsg from CGEN_PARSE_FN */
|
||
if (strlen (start) > 50)
|
||
/* xgettext:c-format */
|
||
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
|
||
else
|
||
/* xgettext:c-format */
|
||
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
|
||
#else
|
||
if (strlen (start) > 50)
|
||
/* xgettext:c-format */
|
||
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
|
||
else
|
||
/* xgettext:c-format */
|
||
sprintf (errbuf, _("bad instruction `%.50s'"), start);
|
||
#endif
|
||
|
||
*errmsg = errbuf;
|
||
return NULL;
|
||
}
|
||
}
|
||
|
||
#if 0 /* This calls back to GAS which we can't do without care. */
|
||
|
||
/* Record each member of OPVALS in the assembler's symbol table.
|
||
This lets GAS parse registers for us.
|
||
??? Interesting idea but not currently used. */
|
||
|
||
/* Record each member of OPVALS in the assembler's symbol table.
|
||
FIXME: Not currently used. */
|
||
|
||
void
|
||
fr30_cgen_asm_hash_keywords (cd, opvals)
|
||
CGEN_CPU_DESC cd;
|
||
CGEN_KEYWORD *opvals;
|
||
{
|
||
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
|
||
const CGEN_KEYWORD_ENTRY * ke;
|
||
|
||
while ((ke = cgen_keyword_search_next (& search)) != NULL)
|
||
{
|
||
#if 0 /* Unnecessary, should be done in the search routine. */
|
||
if (! fr30_cgen_opval_supported (ke))
|
||
continue;
|
||
#endif
|
||
cgen_asm_record_register (cd, ke->name, ke->value);
|
||
}
|
||
}
|
||
|
||
#endif /* 0 */
|