236 lines
6.4 KiB
C
236 lines
6.4 KiB
C
#include "config.h"
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#include <stdio.h>
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#include <ctype.h>
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#include <limits.h>
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#include "ansidecl.h"
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#include "callback.h"
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#include "opcode/d10v.h"
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#include "bfd.h"
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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#define DEBUG_LINE_NUMBER 0x00000004
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#define DEBUG_MEMSIZE 0x00000008
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#define DEBUG_INSTRUCTION 0x00000010
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#ifndef DEBUG
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#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
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#endif
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extern int d10v_debug;
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#include "sim-types.h"
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typedef unsigned8 uint8;
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typedef unsigned16 uint16;
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typedef signed16 int16;
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typedef unsigned32 uint32;
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typedef signed32 int32;
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typedef unsigned64 uint64;
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typedef signed64 int64;
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/* FIXME: D10V defines */
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typedef uint16 reg_t;
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struct simops
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{
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long opcode;
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int is_long;
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long mask;
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int format;
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int cycles;
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int unit;
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int exec_type;
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void (*func)();
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int numops;
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int operands[9];
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};
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enum _ins_type
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{
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INS_UNKNOWN, /* unknown instruction */
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INS_COND_TRUE, /* # times EXExxx executed other instruction */
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INS_COND_FALSE, /* # times EXExxx did not execute other instruction */
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INS_COND_JUMP, /* # times JUMP skipped other instruction */
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INS_CYCLES, /* # cycles */
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INS_LONG, /* long instruction (both containers, ie FM == 11) */
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INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */
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INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */
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INS_PARALLEL, /* # times instruction encoded as L || R (ie, RM == 00) */
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INS_LEFT, /* normal left instructions */
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INS_LEFT_PARALLEL, /* left side of || */
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INS_LEFT_COND_TEST, /* EXExx test on left side */
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INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */
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INS_LEFT_NOPS, /* NOP on left side */
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INS_RIGHT, /* normal right instructions */
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INS_RIGHT_PARALLEL, /* right side of || */
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INS_RIGHT_COND_TEST, /* EXExx test on right side */
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INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */
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INS_RIGHT_NOPS, /* NOP on right side */
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INS_MAX
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};
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extern unsigned long ins_type_counters[ (int)INS_MAX ];
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struct _state
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{
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reg_t regs[16]; /* general-purpose registers */
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reg_t cregs[16]; /* control registers */
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int64 a[2]; /* accumulators */
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uint8 SM;
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uint8 EA;
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uint8 DB;
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uint8 DM;
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uint8 IE;
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uint8 RP;
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uint8 MD;
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uint8 FX;
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uint8 ST;
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uint8 F0;
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uint8 F1;
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uint8 C;
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uint8 exe;
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int exception;
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int pc_changed;
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/* everything below this line is not reset by sim_create_inferior() */
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uint8 *imem;
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uint8 *dmem;
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uint8 *umem[128];
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enum _ins_type ins_type;
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} State;
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extern host_callback *d10v_callback;
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extern uint16 OP[4];
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extern struct simops Simops[];
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extern asection *text;
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extern bfd_vma text_start;
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extern bfd_vma text_end;
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extern bfd *prog_bfd;
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enum
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{
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PSW_CR = 0,
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BPSW_CR = 1,
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PC_CR = 2,
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BPC_CR = 3,
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RPT_C_CR = 7,
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RPT_S_CR = 8,
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RPT_E_CR = 9,
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MOD_S_CR = 10,
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MOD_E_CR = 11,
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IBA_CR = 14,
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};
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enum
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{
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PSW_SM_BIT = 0x8000,
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PSW_EA_BIT = 0x2000,
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PSW_DB_BIT = 0x1000,
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PSW_DM_BIT = 0x0800,
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PSW_IE_BIT = 0x0400,
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PSW_RP_BIT = 0x0200,
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PSW_MD_BIT = 0x0100,
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PSW_FX_BIT = 0x0080,
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PSW_ST_BIT = 0x0040,
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PSW_F0_BIT = 0x0008,
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PSW_F1_BIT = 0x0004,
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PSW_C_BIT = 0x0001,
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};
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/* See simopsc.:move_to_cr() for registers that can not be read-from
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or assigned-to directly */
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#define PC (State.cregs[PC_CR])
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#define PSW (move_from_cr (PSW_CR))
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#define BPSW (0 + State.cregs[PSW_CR])
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#define BPC (State.cregs[BPC_CR])
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#define RPT_C (State.cregs[RPT_C_CR])
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#define RPT_S (State.cregs[RPT_S_CR])
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#define RPT_E (State.cregs[RPT_E_CR])
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#define MOD_S (0 + State.cregs[MOD_S_CR])
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#define MOD_E (0 + State.cregs[MOD_E_CR])
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#define IBA (State.cregs[IBA_CR])
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#define SIG_D10V_STOP -1
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#define SIG_D10V_EXIT -2
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#define SEXT3(x) ((((x)&0x7)^(~3))+4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~7))+8)
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/* sign-extend an 8-bit number */
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#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
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/* sign-extend a 16-bit number */
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
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/* sign extend a 56 bit number */
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#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
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#define MAX32 SIGNED64(0x7fffffff)
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#define MIN32 SIGNED64(0xff80000000)
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#define MASK32 SIGNED64(0xffffffff)
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#define MASK40 SIGNED64(0xffffffffff)
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/* The alignment of MOD_E in the following macro depends upon "i" always being a power of 2. */
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#define INC_ADDR(x,i) x = ((State.MD && x == (MOD_E & ~((i)-1))) ? MOD_S : (x)+(i))
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extern uint8 *dmem_addr PARAMS ((uint32));
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extern bfd_vma decode_pc PARAMS ((void));
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#define RB(x) (*(dmem_addr(x)))
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#define SB(addr,data) ( RB(addr) = (data & 0xff))
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#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
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#define ENDIAN_INLINE static __inline__
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#include "endian.c"
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#undef ENDIAN_INLINE
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#else
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extern uint32 get_longword PARAMS ((uint8 *));
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extern uint16 get_word PARAMS ((uint8 *));
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extern int64 get_longlong PARAMS ((uint8 *));
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extern void write_word PARAMS ((uint8 *addr, uint16 data));
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extern void write_longword PARAMS ((uint8 *addr, uint32 data));
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extern void write_longlong PARAMS ((uint8 *addr, int64 data));
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#endif
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#define SW(addr,data) write_word(dmem_addr(addr),data)
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#define RW(x) get_word(dmem_addr(x))
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#define SLW(addr,data) write_longword(dmem_addr(addr),data)
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#define RLW(x) get_longword(dmem_addr(x))
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#define READ_16(x) get_word(x)
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#define WRITE_16(addr,data) write_word(addr,data)
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#define READ_64(x) get_longlong(x)
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#define WRITE_64(addr,data) write_longlong(addr,data)
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#define IMAP0 RW(0xff00)
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#define IMAP1 RW(0xff02)
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#define DMAP RW(0xff04)
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#define SET_IMAP0(x) SW(0xff00,x)
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#define SET_IMAP1(x) SW(0xff02,x)
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#define SET_DMAP(x) SW(0xff04,x)
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#define JMP(x) { PC = (x); State.pc_changed = 1; }
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#define AE_VECTOR_START 0xffc3
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#define RIE_VECTOR_START 0xffc2
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#define SDBT_VECTOR_START 0xffd5
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#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
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extern void move_to_cr PARAMS ((int cr, reg_t val));
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extern reg_t move_from_cr PARAMS ((int cr));
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