534 lines
18 KiB
C
534 lines
18 KiB
C
/* Copyright (C) 2000, 2003, 2007 Free Software Foundation
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Contributed by Alexandre Oliva <aoliva@cygnus.com>
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/* Generator of tests for Maverick.
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See the following file for usage and documentation. */
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#include "../all/test-gen.c"
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/* These are the ARM registers. Some of them have canonical names
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other than r##, so we'll use both in the asm input, but only the
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canonical names in the expected disassembler output. */
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char *arm_regs[] =
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{
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/* Canonical names. */
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
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/* Alternate names, i.e., those that can be used in the assembler,
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* but that will never be emitted by the disassembler. */
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
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};
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/* The various types of registers: ARM's registers, Maverick's
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f/d/fx/dx registers, Maverick's accumulators and Maverick's
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status register. */
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#define armreg(shift) \
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reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
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#define mvreg(prefix, shift) \
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reg_p ("mv" prefix, shift, mk_get_bits (4u))
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#define acreg(shift) \
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reg_p ("mvax", shift, mk_get_bits (2u))
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#define dspsc \
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literal ("dspsc"), tick_random
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/* This outputs the condition flag that may follow each ARM insn.
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Since the condition 15 is invalid, we use it to check that the
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assembler recognizes the absence of a condition as `al'. However,
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the disassembler won't ever output `al', so, if we emit it in the
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assembler, expect the condition to be omitted in the disassembler
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output. */
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int
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arm_cond (func_arg * arg, insn_data * data)
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#define arm_cond { arm_cond }
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{
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static const char conds[16][3] =
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{
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"eq", "ne", "cs", "cc",
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"mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt",
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"gt", "le", "al", ""
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};
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unsigned val = get_bits (4u);
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data->as_in = data->dis_out = strdup (conds[val]);
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if (val == 14)
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data->dis_out = strdup ("");
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data->bits = (val == 15 ? 14 : val) << 28;
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return 0;
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}
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/* The sign of an offset is actually used to determined whether the
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absolute value of the offset should be added or subtracted, so we
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must adjust negative values so that they do not overflow: -1024 is
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not valid, but -0 is distinct from +0. */
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int
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off8s (func_arg * arg, insn_data * data)
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#define off8s { off8s }
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{
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int val;
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char value[9];
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/* Zero values are problematical.
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The assembler performs translations on the addressing modes
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for these values, meaning that we cannot just recreate the
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disassembler string in the LDST macro without knowing what
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value had been generated in off8s. */
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do
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{
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val = get_bits (9s);
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}
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while (val == -1 || val == 0);
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val <<= 2;
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if (val < 0)
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{
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val = -4 - val;
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sprintf (value, ", #-%i", val);
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data->dis_out = strdup (value);
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sprintf (value, ", #-%i", val);
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data->as_in = strdup (value);
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data->bits = val >> 2;
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}
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else
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{
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sprintf (value, ", #%i", val);
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data->as_in = data->dis_out = strdup (value);
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data->bits = (val >> 2) | (1 << 23);
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}
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return 0;
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}
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/* This function generates a 7-bit signed constant, emitted as
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follows: the 4 least-significant bits are stored in the 4
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least-significant bits of the word; the 3 most-significant bits are
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stored in bits 7:5, i.e., bit 4 is skipped. */
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int
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imm7 (func_arg *arg, insn_data *data)
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#define imm7 { imm7 }
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{
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int val = get_bits (7s);
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char value[6];
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data->bits = (val & 0x0f) | (2 * (val & 0x70));
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sprintf (value, "#%i", val);
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data->as_in = data->dis_out = strdup (value);
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return 0;
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}
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/* Convenience wrapper to define_insn, that prefixes every insn with
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`cf' (so, if you specify command-line arguments, remember that `cf'
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must *not* be part of the string), and post-fixes a condition code.
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insname and insnvar specify the main insn name and a variant;
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they're just concatenated, and insnvar is often empty. word is the
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bit pattern that defines the insn, properly shifted, and funcs is a
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sequence of funcs that define the operands and the syntax of the
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insn. */
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#define mv_insn(insname, insnvar, word, funcs...) \
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define_insn (insname ## insnvar, \
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literal ("cf"), \
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insn_bits (insname, word), \
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arm_cond, \
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tab, \
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## funcs)
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/* Define a single LDC/STC variant. op is the main insn opcode; ld
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stands for load (it should be 0 on stores), dword selects 64-bit
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operations, pre should be enabled for pre-increment, and wb, for
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write-back. sep1, sep2 and sep3 are syntactical elements ([]!)
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that the assembler will use to enable pre and wb. It would
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probably have been cleaner to couple the syntactical elements with
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the pre/wb bits directly, but it would have required the definition
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of more functions. */
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#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \
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mv_insn (insname, insnvar, \
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(12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \
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mvreg (regname, 12), comma, \
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lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \
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tick_random)
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/* Define all variants of an LDR or STR instruction, namely,
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pre-indexed without write-back, pre-indexed with write-back and
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post-indexed. */
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#define LDSTall(insname, op, ld, dword, regname) \
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LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
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LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \
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LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing)
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/* Produce the insn identifiers of all LDST variants of a given insn.
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To be used in the initialization of an insn group array. */
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#define insns_LDSTall(insname) \
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insn (insname ## _p), insn (insname ## _pw), insn (insname)
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/* Define a CDP variant that uses two registers, at offsets 12 and 16.
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The two opcodes and the co-processor number identify the CDP
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insn. */
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#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
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mv_insn (insname##var, , \
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(14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
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mvreg (reg1name, 12), comma, mvreg (reg2name, 16))
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/* Define a 32-bit integer CDP instruction with two operands. */
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#define CDP2fx(insname, opcode1, opcode2) \
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CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
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/* Define a 64-bit integer CDP instruction with two operands. */
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#define CDP2dx(insname, opcode1, opcode2) \
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CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
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/* Define a float CDP instruction with two operands. */
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#define CDP2f(insname, opcode1, opcode2) \
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CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
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/* Define a double CDP instruction with two operands. */
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#define CDP2d(insname, opcode1, opcode2) \
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CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")
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/* Define a CDP instruction with two register operands and one 7-bit
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signed immediate generated with imm7. */
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#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \
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mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \
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mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
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tick_random)
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/* Produce the insn identifiers of CDP floating-point or integer insn
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pairs (i.e., it appends the suffixes for 32-bit and 64-bit
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insns. */
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#define CDPfp_insns(insname) \
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insn (insname ## s), insn (insname ## d)
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#define CDPx_insns(insname) \
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insn (insname ## 32), insn (insname ## 64)
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/* Define a CDP instruction with 3 operands, at offsets 12, 16, 0. */
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#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \
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mv_insn (insname##var, , \
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(14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
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mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
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mvreg (reg3name, 0), tick_random)
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/* Define a 32-bit integer CDP instruction with three operands. */
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#define CDP3fx(insname, opcode1, opcode2) \
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CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")
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/* Define a 64-bit integer CDP instruction with three operands. */
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#define CDP3dx(insname, opcode1, opcode2) \
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CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")
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/* Define a float CDP instruction with three operands. */
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#define CDP3f(insname, opcode1, opcode2) \
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CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")
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/* Define a double CDP instruction with three operands. */
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#define CDP3d(insname, opcode1, opcode2) \
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CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")
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/* Define a CDP instruction with four operands, at offsets 5, 12, 16
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* and 0. Used only for ACC instructions. */
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#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \
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mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \
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acreg (5), comma, reg2spec, comma, \
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mvreg (reg3name, 16), comma, mvreg (reg4name, 0))
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/* Define a CDP4 instruction with one accumulator operands. */
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#define CDP41A(insname, opcode1) \
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CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")
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/* Define a CDP4 instruction with two accumulator operands. */
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#define CDP42A(insname, opcode1) \
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CDP4 (insname, opcode1, acreg (12), "fx", "fx")
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/* Define a MCR or MRC instruction with two register operands. */
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#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \
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mv_insn (insname, , \
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((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
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((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
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reg1spec, comma, reg2spec)
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/* Define a move from a DSP register to an ARM register. */
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#define MVDSPARM(insname, cpnum, opcode2, regDSPname) \
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MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
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mvreg (regDSPname, 16), armreg (12))
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/* Define a move from an ARM register to a DSP register. */
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#define MVARMDSP(insname, cpnum, opcode2, regDSPname) \
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MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
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armreg (12), mvreg (regDSPname, 16))
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/* Move between coprocessor registers. A two operand CDP insn. */
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#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \
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mv_insn (insname, , \
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((14 << 24) | ((opcode1) << 20) | \
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(4 << 8) | ((opcode2) << 5)), \
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reg1spec, comma, reg2spec)
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/* Define a move from a DSP register to a DSP accumulator. */
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#define MVDSPACC(insname, opcode2, regDSPname) \
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MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))
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/* Define a move from a DSP accumulator to a DSP register. */
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#define MVACCDSP(insname, opcode2, regDSPname) \
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MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))
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/* Define move insns between a float DSP register and an ARM
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register. */
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#define MVf(nameAD, nameDA, opcode2) \
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MVDSPARM (nameAD, 4, opcode2, "f"); \
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MVARMDSP (nameDA, 4, opcode2, "f")
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/* Define move insns between a double DSP register and an ARM
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register. */
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#define MVd(nameAD, nameDA, opcode2) \
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MVDSPARM (nameAD, 4, opcode2, "d"); \
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MVARMDSP (nameDA, 4, opcode2, "d")
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/* Define move insns between a 32-bit integer DSP register and an ARM
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register. */
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#define MVfx(nameAD, nameDA, opcode2) \
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MVDSPARM (nameAD, 5, opcode2, "fx"); \
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MVARMDSP (nameDA, 5, opcode2, "fx")
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/* Define move insns between a 64-bit integer DSP register and an ARM
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register. */
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#define MVdx(nameAD, nameDA, opcode2) \
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MVDSPARM (nameAD, 5, opcode2, "dx"); \
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MVARMDSP (nameDA, 5, opcode2, "dx")
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/* Define move insns between a 32-bit DSP register and a DSP
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accumulator. */
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#define MVfxa(nameFA, nameAF, opcode2) \
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MVDSPACC (nameFA, opcode2, "fx"); \
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MVACCDSP (nameAF, opcode2, "fx")
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/* Define move insns between a 64-bit DSP register and a DSP
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accumulator. */
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#define MVdxa(nameDA, nameAD, opcode2) \
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MVDSPACC (nameDA, opcode2, "dx"); \
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MVACCDSP (nameAD, opcode2, "dx")
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/* Produce the insn identifiers for a pair of mv insns. */
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#define insns_MV(name1, name2) \
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insn (mv ## name1), insn (mv ## name2)
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/* Define a MCR or MRC instruction with three register operands. */
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#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
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mv_insn (insname, , \
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((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
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((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
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reg1spec, comma, reg2spec, comma, reg3spec, \
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tick_random)
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/* Define all load_store insns. */
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LDSTall (ldrs, 4, 1, 0, "f");
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LDSTall (ldrd, 4, 1, 1, "d");
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LDSTall (ldr32, 5, 1, 0, "fx");
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LDSTall (ldr64, 5, 1, 1, "dx");
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LDSTall (strs, 4, 0, 0, "f");
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LDSTall (strd, 4, 0, 1, "d");
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LDSTall (str32, 5, 0, 0, "fx");
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LDSTall (str64, 5, 0, 1, "dx");
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/* Create the load_store insn group. */
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func *load_store_insns[] =
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{
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insns_LDSTall (ldrs), insns_LDSTall (ldrd),
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insns_LDSTall (ldr32), insns_LDSTall (ldr64),
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insns_LDSTall (strs), insns_LDSTall (strd),
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insns_LDSTall (str32), insns_LDSTall (str64),
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0
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};
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/* Define all move insns. */
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MVf (sr, rs, 2);
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MVd (dlr, rdl, 0);
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MVd (dhr, rdh, 1);
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MVdx (64lr, r64l, 0);
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MVdx (64hr, r64h, 1);
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MVfxa (al32, 32al, 2);
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MVfxa (am32, 32am, 3);
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MVfxa (ah32, 32ah, 4);
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MVfxa (a32, 32a, 5);
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MVdxa (a64, 64a, 6);
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MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12));
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MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc);
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CDP2 (cpys, , 4, 0, 0, "f", "f");
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CDP2 (cpyd, , 4, 0, 1, "d", "d");
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/* Create the move insns group. */
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func * move_insns[] =
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{
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insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
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insns_MV (64lr, r64l), insns_MV (64hr, r64h),
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insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
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insns_MV (a32, 32a), insns_MV (a64, 64a),
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insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
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0
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};
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/* Define all conversion insns. */
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CDP2 (cvtsd, , 4, 0, 3, "d", "f");
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CDP2 (cvtds, , 4, 0, 2, "f", "d");
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CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
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CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
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CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
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CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
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CDP2 (cvts32, , 5, 1, 4, "fx", "f");
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CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
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CDP2 (truncs32, , 5, 1, 6, "fx", "f");
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CDP2 (truncd32, , 5, 1, 7, "fx", "d");
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/* Create the conv insns group. */
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func * conv_insns[] =
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{
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insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
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insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
|
|
insn (truncs32), insn (truncd32),
|
|
0
|
|
};
|
|
|
|
/* Define all shift insns. */
|
|
MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12));
|
|
MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12));
|
|
CDP2_imm7 (sh32, 5, 0, "fx", "fx");
|
|
CDP2_imm7 (sh64, 5, 2, "dx", "dx");
|
|
|
|
/* Create the shift insns group. */
|
|
func *shift_insns[] =
|
|
{
|
|
insn (rshl32), insn (rshl64),
|
|
insn (sh32), insn (sh64),
|
|
0
|
|
};
|
|
|
|
/* Define all comparison insns. */
|
|
MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
|
|
MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
|
|
MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
|
|
MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));
|
|
|
|
/* Create the comp insns group. */
|
|
func *comp_insns[] =
|
|
{
|
|
insn (cmps), insn (cmpd),
|
|
insn (cmp32), insn (cmp64),
|
|
0
|
|
};
|
|
|
|
/* Define all floating-point arithmetic insns. */
|
|
CDP2f (abs, 3, 0);
|
|
CDP2d (abs, 3, 1);
|
|
CDP2f (neg, 3, 2);
|
|
CDP2d (neg, 3, 3);
|
|
CDP3f (add, 3, 4);
|
|
CDP3d (add, 3, 5);
|
|
CDP3f (sub, 3, 6);
|
|
CDP3d (sub, 3, 7);
|
|
CDP3f (mul, 1, 0);
|
|
CDP3d (mul, 1, 1);
|
|
|
|
/* Create the fp-arith insns group. */
|
|
func *fp_arith_insns[] =
|
|
{
|
|
CDPfp_insns (abs), CDPfp_insns (neg),
|
|
CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
|
|
0
|
|
};
|
|
|
|
/* Define all integer arithmetic insns. */
|
|
CDP2fx (abs, 3, 0);
|
|
CDP2dx (abs, 3, 1);
|
|
CDP2fx (neg, 3, 2);
|
|
CDP2dx (neg, 3, 3);
|
|
CDP3fx (add, 3, 4);
|
|
CDP3dx (add, 3, 5);
|
|
CDP3fx (sub, 3, 6);
|
|
CDP3dx (sub, 3, 7);
|
|
CDP3fx (mul, 1, 0);
|
|
CDP3dx (mul, 1, 1);
|
|
CDP3fx (mac, 1, 2);
|
|
CDP3fx (msc, 1, 3);
|
|
|
|
/* Create the int-arith insns group. */
|
|
func * int_arith_insns[] =
|
|
{
|
|
CDPx_insns (abs), CDPx_insns (neg),
|
|
CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
|
|
insn (mac32), insn (msc32),
|
|
0
|
|
};
|
|
|
|
/* Define all accumulator arithmetic insns. */
|
|
CDP41A (madd32, 0);
|
|
CDP41A (msub32, 1);
|
|
CDP42A (madda32, 2);
|
|
CDP42A (msuba32, 3);
|
|
|
|
/* Create the acc-arith insns group. */
|
|
func * acc_arith_insns[] =
|
|
{
|
|
insn (madd32), insn (msub32),
|
|
insn (madda32), insn (msuba32),
|
|
0
|
|
};
|
|
|
|
/* Create the set of all groups. */
|
|
group_t groups[] =
|
|
{
|
|
{ "load_store", load_store_insns },
|
|
{ "move", move_insns },
|
|
{ "conv", conv_insns },
|
|
{ "shift", shift_insns },
|
|
{ "comp", comp_insns },
|
|
{ "fp_arith", fp_arith_insns },
|
|
{ "int_arith", int_arith_insns },
|
|
{ "acc_arith", acc_arith_insns },
|
|
{ 0 }
|
|
};
|
|
|
|
int
|
|
main (int argc, char *argv[])
|
|
{
|
|
FILE *as_in = stdout, *dis_out = stderr;
|
|
|
|
/* Check whether we're filtering insns. */
|
|
if (argc > 1)
|
|
skip_list = argv + 1;
|
|
|
|
/* Output assembler header. */
|
|
fputs ("\t.text\n"
|
|
"\t.align\n",
|
|
as_in);
|
|
/* Output comments for the testsuite-driver and the initial
|
|
disassembler output. */
|
|
fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
|
|
"#name: Maverick\n"
|
|
"#as: -mcpu=ep9312\n"
|
|
"\n"
|
|
"# Test the instructions of the Cirrus Maverick floating point co-processor\n"
|
|
"\n"
|
|
".*: +file format.*arm.*\n"
|
|
"\n"
|
|
"Disassembly of section .text:\n",
|
|
dis_out);
|
|
|
|
/* Now emit all (selected) insns. */
|
|
output_groups (groups, as_in, dis_out);
|
|
|
|
exit (0);
|
|
}
|