Andrew Cagney c357e16ac8 * dv-mn103int.c (decode_group): A group register every 4 bytes not 8. ... (write_icr): Rewrite equation updating request field. (read_iagr): Fix check that interrupt is still pending.		1998-03-25 14:52:44 +00:00
..
.Sanitize	* interp.c (sim_open): Tidy up device creation.	1998-03-25 05:37:42 +00:00
ChangeLog	* dv-mn103int.c (decode_group): A group register every 4 bytes not 8.	1998-03-25 14:52:44 +00:00
config.in	Get configure to define RETSIGTYPE	1997-04-07 05:58:59 +00:00
configure	* interp.c (sim_open): Create second 1mb memory region at 0x40000000.	1998-03-25 04:15:38 +00:00
configure.in	* interp.c (sim_open): Create second 1mb memory region at 0x40000000.	1998-03-25 04:15:38 +00:00
dv-mn103cpu.c	* interp.c (sim_open): Create second 1mb memory region at 0x40000000.	1998-03-25 04:15:38 +00:00
dv-mn103int.c	* interp.c (sim_open): Tidy up device creation.	1998-03-25 05:37:42 +00:00
gencode.c	* gencode.c (write_opcodes): Also write out the format of the	1996-12-11 16:58:33 +00:00
interp.c	* interp.c (sim_open): Create second 1mb memory region at 0x40000000.	1998-03-25 04:15:38 +00:00
Makefile.in	Add support for building simulator based on common simulator framework.	1998-03-24 20:19:55 +00:00
mn10300.dc	IGEN input files for mn10300 simulator.	1998-03-24 20:07:22 +00:00
mn10300.igen	Pacify GCC.	1998-03-25 00:08:52 +00:00
mn10300_sim.h	Pacify GCC.	1998-03-25 00:08:52 +00:00
sim-main.h	Header file required by igen generated files.	1998-03-24 20:08:00 +00:00
simops.c	* simops.c (inc): Fix typo.	1998-02-28 01:41:28 +00:00