913 lines
18 KiB
C
913 lines
18 KiB
C
#include <signal.h>
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#include "sim-main.h"
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#include "sim-options.h"
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#include "v850_sim.h"
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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#ifdef HAVE_STRING_H
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#include <string.h>
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#else
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#ifdef HAVE_STRINGS_H
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#include <strings.h>
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#endif
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#endif
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#include "bfd.h"
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/* For compatibility */
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SIM_DESC simulator;
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enum interrupt_type
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{
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int_none,
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int_reset,
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int_nmi,
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int_intov1,
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int_intp10,
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int_intp11,
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int_intp12,
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int_intp13,
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int_intcm4,
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num_int_types
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};
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enum interrupt_cond_type
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{
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int_cond_none,
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int_cond_pc,
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int_cond_time
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};
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struct interrupt_generator
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{
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enum interrupt_type type;
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enum interrupt_cond_type cond_type;
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int number;
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SIM_ADDR address;
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unsigned long time;
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int enabled;
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struct interrupt_generator *next;
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};
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char *interrupt_names[] = {
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"",
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"reset",
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"nmi",
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"intov1",
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"intp10",
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"intp11",
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"intp12",
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"intp13",
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"intcm4",
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NULL
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};
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struct interrupt_generator *intgen_list;
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/* True if a non-maskable (such as NMI or reset) interrupt generator
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is present. */
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static int have_nm_generator;
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#ifndef INLINE
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#ifdef __GNUC__
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#define INLINE inline
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#else
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#define INLINE
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#endif
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#endif
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/* These default values correspond to expected usage for the chip. */
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int v850_debug;
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uint32 OP[4];
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static struct hash_entry *lookup_hash PARAMS ((SIM_DESC sd, uint32 ins));
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static long hash PARAMS ((long));
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#if 0
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static void do_format_1_2 PARAMS ((uint32));
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static void do_format_3 PARAMS ((uint32));
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static void do_format_4 PARAMS ((uint32));
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static void do_format_5 PARAMS ((uint32));
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static void do_format_6 PARAMS ((uint32));
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static void do_format_7 PARAMS ((uint32));
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static void do_format_8 PARAMS ((uint32));
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static void do_format_9_10 PARAMS ((uint32));
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#endif
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#define MAX_HASH 63
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struct hash_entry
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{
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struct hash_entry *next;
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unsigned long opcode;
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unsigned long mask;
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struct simops *ops;
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};
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struct hash_entry hash_table[MAX_HASH+1];
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static INLINE long
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hash(insn)
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long insn;
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{
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if ( (insn & 0x0600) == 0
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|| (insn & 0x0700) == 0x0200
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|| (insn & 0x0700) == 0x0600
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|| (insn & 0x0780) == 0x0700)
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return (insn & 0x07e0) >> 5;
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if ((insn & 0x0700) == 0x0300
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|| (insn & 0x0700) == 0x0400
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|| (insn & 0x0700) == 0x0500)
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return (insn & 0x0780) >> 7;
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if ((insn & 0x07c0) == 0x0780)
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return (insn & 0x07c0) >> 6;
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return (insn & 0x07e0) >> 5;
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}
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static struct hash_entry *
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lookup_hash (sd, ins)
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SIM_DESC sd;
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uint32 ins;
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{
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struct hash_entry *h;
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h = &hash_table[hash(ins)];
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while ((ins & h->mask) != h->opcode)
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{
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if (h->next == NULL)
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{
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sim_io_error (sd, "ERROR looking up hash for 0x%lx, PC=0x%lx",
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(long) ins, (long) PC);
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}
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h = h->next;
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}
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return (h);
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}
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/* FIXME These would more efficient to use than load_mem/store_mem,
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but need to be changed to use the memory map. */
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uint8
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get_byte (x)
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uint8 *x;
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{
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return *x;
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}
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uint16
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get_half (x)
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uint8 *x;
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{
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uint8 *a = x;
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return (a[1] << 8) + (a[0]);
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}
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uint32
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get_word (x)
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uint8 *x;
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{
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uint8 *a = x;
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return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
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}
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void
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put_byte (addr, data)
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uint8 *addr;
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uint8 data;
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{
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uint8 *a = addr;
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a[0] = data;
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}
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void
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put_half (addr, data)
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uint8 *addr;
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uint16 data;
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{
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uint8 *a = addr;
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a[0] = data & 0xff;
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a[1] = (data >> 8) & 0xff;
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}
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void
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put_word (addr, data)
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uint8 *addr;
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uint32 data;
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{
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uint8 *a = addr;
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a[0] = data & 0xff;
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a[1] = (data >> 8) & 0xff;
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a[2] = (data >> 16) & 0xff;
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a[3] = (data >> 24) & 0xff;
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}
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uint8 *
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map (addr)
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SIM_ADDR addr;
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{
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/* Mask down to 24 bits. */
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addr &= 0xffffff;
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if (addr < 0x100000)
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{
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/* "Mirror" the addresses below 1MB. */
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addr = addr & (simulator->rom_size - 1);
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return (uint8 *) (simulator->mem) + addr;
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}
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else if (addr < simulator->low_end)
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{
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/* chunk is just after the rom */
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addr = addr - 0x100000 + simulator->rom_size;
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return (uint8 *) (simulator->mem) + addr;
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}
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else if (addr >= simulator->high_start)
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{
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/* If in the peripheral I/O region, mirror 1K region across 4K,
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and similarly if in the internal RAM region. */
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if (addr >= 0xfff000)
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addr &= 0xfff3ff;
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else if (addr >= 0xffe000)
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addr &= 0xffe3ff;
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addr = addr - simulator->high_start + simulator->high_base;
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return (uint8 *) (simulator->mem) + addr;
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}
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else
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{
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sim_io_eprintf (simulator, "segmentation fault: access address: %lx not below %lx or above %lx [ep = %lx]\n",
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(long) addr,
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(long) simulator->low_end,
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(long) simulator->high_start,
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State.regs[30]);
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/* Signal a memory error. */
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State.exception = SIGSEGV;
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/* Point to a location not in main memory - renders invalid
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addresses harmless until we get back to main insn loop. */
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return (uint8 *) &(State.dummy_mem);
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}
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}
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uint32
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load_mem (addr, len)
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SIM_ADDR addr;
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int len;
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{
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uint8 *p = map (addr);
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switch (len)
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{
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case 1:
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return p[0];
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case 2:
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return p[1] << 8 | p[0];
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case 4:
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return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
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default:
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abort ();
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}
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}
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void
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store_mem (addr, len, data)
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SIM_ADDR addr;
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int len;
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uint32 data;
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{
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uint8 *p = map (addr);
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switch (len)
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{
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case 1:
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p[0] = data;
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return;
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case 2:
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p[0] = data;
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p[1] = data >> 8;
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return;
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case 4:
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p[0] = data;
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p[1] = data >> 8;
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p[2] = data >> 16;
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p[3] = data >> 24;
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return;
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default:
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abort ();
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}
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}
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static void
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sim_memory_init (SIM_DESC sd)
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{
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int totsize;
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if (sd->mem)
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zfree (sd->mem);
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totsize = (simulator->rom_size
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+ (sd->low_end - 0x100000)
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+ (0x1000000 - sd->high_start));
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sd->high_base = sd->rom_size + (sd->low_end - 0x100000);
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sd->mem = zalloc (totsize);
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if (!sd->mem)
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{
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sim_io_error (sd, "Allocation of main memory failed.");
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}
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}
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static int
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sim_parse_number (str, rest)
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char *str, **rest;
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{
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if (str[0] == '0' && str[1] == 'x')
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return strtoul (str, rest, 16);
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else if (str[0] == '0')
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return strtoul (str, rest, 16);
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else
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return strtoul (str, rest, 10);
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}
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static void
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sim_set_memory_map (sd, spec)
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SIM_DESC sd;
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char *spec;
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{
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char *reststr, *nreststr;
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SIM_ADDR new_low_end, new_high_start;
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new_low_end = sd->low_end;
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new_high_start = sd->high_start;
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if (! strncmp (spec, "hole=", 5))
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{
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new_low_end = sim_parse_number (spec + 5, &reststr);
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if (new_low_end < 0x100000)
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{
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sim_io_printf (sd, "Low end must be at least 0x100000\n");
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return;
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}
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if (*reststr == ',')
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{
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++reststr;
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new_high_start = sim_parse_number (reststr, &nreststr);
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/* FIXME Check high_start also */
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}
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sim_io_printf (sd, "Hole goes from 0x%x to 0x%x\n",
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new_low_end, new_high_start);
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}
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else
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{
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sim_io_printf (sd, "Invalid specification for memory map, must be `hole=<m>[,<n>]'\n");
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}
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if (new_low_end != sd->low_end || new_high_start != sd->high_start)
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{
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sd->low_end = new_low_end;
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sd->high_start = new_high_start;
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sim_io_printf (sd, "Reconfiguring memory (old contents will be lost)\n");
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sim_memory_init (sd);
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}
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}
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/* Parse a number in hex, octal, or decimal form. */
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int
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sim_write (sd, addr, buffer, size)
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SIM_DESC sd;
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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{
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int i;
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for (i = 0; i < size; i++)
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store_mem (addr + i, 1, buffer[i]);
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return size;
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}
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SIM_DESC
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sim_open (kind, cb, abfd, argv)
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SIM_OPEN_KIND kind;
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host_callback *cb;
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struct _bfd *abfd;
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char **argv;
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{
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SIM_DESC sd = sim_state_alloc (kind, cb);
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struct simops *s;
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struct hash_entry *h;
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/* for compatibility */
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simulator = sd;
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sd->rom_size = V850_ROM_SIZE;
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sd->low_end = V850_LOW_END;
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sd->high_start = V850_HIGH_START;
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/* Allocate memory */
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sim_memory_init (sd);
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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return 0;
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/* getopt will print the error message so we just have to exit if this fails.
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FIXME: Hmmm... in the case of gdb we need getopt to call
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print_filtered. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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/* check for/establish the a reference program image */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL),
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abfd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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/* establish any remaining configuration options */
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if (sim_config (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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/* put all the opcodes in the hash table */
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for (s = Simops; s->func; s++)
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{
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h = &hash_table[hash(s->opcode)];
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/* go to the last entry in the chain */
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while (h->next)
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h = h->next;
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if (h->ops)
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{
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h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
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h = h->next;
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}
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h->ops = s;
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h->mask = s->mask;
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h->opcode = s->opcode;
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}
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return sd;
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}
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void
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sim_close (sd, quitting)
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SIM_DESC sd;
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int quitting;
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{
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sim_module_uninstall (sd);
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}
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static void do_interrupt PARAMS ((SIM_DESC sd, enum interrupt_type));
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int
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sim_stop (sd)
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SIM_DESC sd;
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{
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return 0;
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}
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void
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sim_resume (sd, step, siggnal)
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SIM_DESC sd;
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int step, siggnal;
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{
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SIM_ELAPSED_TIME start_time;
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uint32 inst;
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SIM_ADDR oldpc;
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struct interrupt_generator *intgen;
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if (step)
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State.exception = SIGTRAP;
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else
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State.exception = 0;
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start_time = sim_elapsed_time_get ();
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do
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{
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struct hash_entry * h;
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/* Fetch the current instruction. */
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inst = RLW (PC);
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oldpc = PC;
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h = lookup_hash (sd, inst);
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OP[0] = inst & 0x1f;
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OP[1] = (inst >> 11) & 0x1f;
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OP[2] = (inst >> 16) & 0xffff;
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OP[3] = inst;
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/* fprintf (stderr, "PC = %x, SP = %x\n", PC, SP ); */
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if (inst == 0)
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{
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fprintf (stderr, "NOP encountered!\n");
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break;
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}
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PC += h->ops->func ();
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if (oldpc == PC)
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{
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sim_io_eprintf (sd, "simulator loop at %lx\n", (long) PC );
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break;
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}
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/* Check for and handle pending interrupts. */
|
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if (intgen_list && (have_nm_generator || !(PSW & PSW_ID)))
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{
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intgen = NULL;
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for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
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{
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if (intgen->cond_type == int_cond_pc
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&& oldpc == intgen->address
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&& intgen->enabled)
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{
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break;
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}
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else if (intgen->cond_type == int_cond_time
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&& intgen->enabled)
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{
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SIM_ELAPSED_TIME delta;
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delta = sim_elapsed_time_since (start_time);
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if (delta > intgen->time)
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{
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intgen->enabled = 0;
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break;
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}
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}
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}
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if (intgen)
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do_interrupt (sd, intgen->type);
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}
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else if (State.pending_nmi)
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{
|
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State.pending_nmi = 0;
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do_interrupt (sd, int_nmi);
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}
|
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}
|
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while (!State.exception);
|
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}
|
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|
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static void
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do_interrupt (sd, inttype)
|
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SIM_DESC sd;
|
|
enum interrupt_type inttype;
|
|
{
|
|
/* Disable further interrupts. */
|
|
PSW |= PSW_ID;
|
|
/* Indicate that we're doing interrupt not exception processing. */
|
|
PSW &= ~PSW_EP;
|
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if (inttype == int_reset)
|
|
{
|
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PC = 0;
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PSW = 0x20;
|
|
ECR = 0;
|
|
/* (Might be useful to init other regs with random values.) */
|
|
}
|
|
else if (inttype == int_nmi)
|
|
{
|
|
if (PSW & PSW_NP)
|
|
{
|
|
/* We're already working on an NMI, so this one must wait
|
|
around until the previous one is done. The processor
|
|
ignores subsequent NMIs, so we don't need to count them. */
|
|
State.pending_nmi = 1;
|
|
}
|
|
else
|
|
{
|
|
FEPC = PC;
|
|
FEPSW = PSW;
|
|
/* Set the FECC part of the ECR. */
|
|
ECR &= 0x0000ffff;
|
|
ECR |= 0x10;
|
|
PSW |= PSW_NP;
|
|
PC = 0x10;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
EIPC = PC;
|
|
EIPSW = PSW;
|
|
/* Clear the EICC part of the ECR, will set below. */
|
|
ECR &= 0xffff0000;
|
|
switch (inttype)
|
|
{
|
|
case int_intov1:
|
|
PC = 0x80;
|
|
ECR |= 0x80;
|
|
break;
|
|
case int_intp10:
|
|
PC = 0x90;
|
|
ECR |= 0x90;
|
|
break;
|
|
case int_intp11:
|
|
PC = 0xa0;
|
|
ECR |= 0xa0;
|
|
break;
|
|
case int_intp12:
|
|
PC = 0xb0;
|
|
ECR |= 0xb0;
|
|
break;
|
|
case int_intp13:
|
|
PC = 0xc0;
|
|
ECR |= 0xc0;
|
|
break;
|
|
case int_intcm4:
|
|
PC = 0xd0;
|
|
ECR |= 0xd0;
|
|
break;
|
|
default:
|
|
/* Should never be possible. */
|
|
abort ();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
int
|
|
sim_trace (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
#ifdef DEBUG
|
|
v850_debug = DEBUG;
|
|
#endif
|
|
sim_resume (sd, 0, 0);
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
sim_info (sd, verbose)
|
|
SIM_DESC sd;
|
|
int verbose;
|
|
{
|
|
sim_io_printf (sd, "sim_info\n");
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (sd, prog_bfd, argv, env)
|
|
SIM_DESC sd;
|
|
struct _bfd *prog_bfd;
|
|
char **argv;
|
|
char **env;
|
|
{
|
|
memset (&State, 0, sizeof (State));
|
|
if (prog_bfd != NULL)
|
|
PC = bfd_get_start_address (prog_bfd);
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
/* All the code for exiting, signals, etc needs to be revamped.
|
|
|
|
This is enough to get c-torture limping though. */
|
|
|
|
void
|
|
sim_stop_reason (sd, reason, sigrc)
|
|
SIM_DESC sd;
|
|
enum sim_stop *reason;
|
|
int *sigrc;
|
|
{
|
|
if (State.exception == SIG_V850_EXIT)
|
|
{
|
|
*reason = sim_exited;
|
|
*sigrc = State.regs[7];
|
|
}
|
|
else
|
|
{
|
|
*reason = sim_stopped;
|
|
*sigrc = State.exception;
|
|
}
|
|
}
|
|
|
|
void
|
|
sim_fetch_register (sd, rn, memory)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char *memory;
|
|
{
|
|
put_word (memory, State.regs[rn]);
|
|
}
|
|
|
|
void
|
|
sim_store_register (sd, rn, memory)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char *memory;
|
|
{
|
|
State.regs[rn] = get_word (memory);
|
|
}
|
|
|
|
int
|
|
sim_read (sd, addr, buffer, size)
|
|
SIM_DESC sd;
|
|
SIM_ADDR addr;
|
|
unsigned char *buffer;
|
|
int size;
|
|
{
|
|
int i;
|
|
for (i = 0; i < size; i++)
|
|
buffer[i] = load_mem (addr + i, 1);
|
|
|
|
return size;
|
|
}
|
|
|
|
int current_intgen_number = 1;
|
|
|
|
static void
|
|
sim_set_interrupt (sd, spec)
|
|
SIM_DESC sd;
|
|
char *spec;
|
|
{
|
|
int i, num;
|
|
char **argv;
|
|
struct interrupt_generator *intgen, *tmpgen;
|
|
extern char **buildargv ();
|
|
|
|
argv = buildargv (spec);
|
|
|
|
if (*argv && ! strcmp (*argv, "add"))
|
|
{
|
|
/* Create a new interrupt generator object. */
|
|
intgen = (struct interrupt_generator *)
|
|
malloc (sizeof(struct interrupt_generator));
|
|
intgen->type = int_none;
|
|
intgen->cond_type = int_cond_none;
|
|
intgen->address = 0;
|
|
intgen->time = 0;
|
|
intgen->enabled = 0;
|
|
++argv;
|
|
/* Match on interrupt type name. */
|
|
for (i = 0; i < num_int_types; ++i)
|
|
{
|
|
if (*argv && ! strcmp (*argv, interrupt_names[i]))
|
|
{
|
|
intgen->type = i;
|
|
break;
|
|
}
|
|
}
|
|
if (intgen->type == int_none)
|
|
{
|
|
sim_io_printf (sd, "Interrupt type unknown; known types are\n");
|
|
for (i = 0; i < num_int_types; ++i)
|
|
{
|
|
sim_io_printf (sd, " %s", interrupt_names[i]);
|
|
}
|
|
sim_io_printf (sd, "\n");
|
|
free (intgen);
|
|
return;
|
|
}
|
|
++argv;
|
|
intgen->address = 0;
|
|
intgen->time = 0;
|
|
if (*argv && ! strcmp (*argv, "pc"))
|
|
{
|
|
intgen->cond_type = int_cond_pc;
|
|
++argv;
|
|
intgen->address = sim_parse_number (*argv, NULL);
|
|
}
|
|
else if (*argv && ! strcmp (*argv, "time"))
|
|
{
|
|
intgen->cond_type = int_cond_time;
|
|
++argv;
|
|
intgen->time = sim_parse_number (*argv, NULL);
|
|
}
|
|
else
|
|
{
|
|
sim_io_printf (sd, "Condition type must be `pc' or `time'.\n");
|
|
free (intgen);
|
|
return;
|
|
}
|
|
/* We now have a valid interrupt generator. Number it and add
|
|
to the list of generators. */
|
|
intgen->number = current_intgen_number++;
|
|
intgen->enabled = 1;
|
|
intgen->next = intgen_list;
|
|
intgen_list = intgen;
|
|
sim_io_printf (sd, "Interrupt generator %d (NMI) at pc=0x%x, time=%ld.\n", intgen_list->number, intgen_list->address, intgen_list->time);
|
|
}
|
|
else if (*argv && !strcmp (*argv, "remove"))
|
|
{
|
|
++argv;
|
|
num = sim_parse_number (*argv, NULL);
|
|
tmpgen = NULL;
|
|
if (intgen_list)
|
|
{
|
|
if (intgen_list->number == num)
|
|
{
|
|
tmpgen = intgen_list;
|
|
intgen_list = intgen_list->next;
|
|
}
|
|
else
|
|
{
|
|
for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
|
|
{
|
|
if (intgen->next != NULL && intgen->next->number == num)
|
|
{
|
|
tmpgen = intgen->next;
|
|
intgen->next = intgen->next->next;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
if (tmpgen)
|
|
free (tmpgen);
|
|
else
|
|
sim_io_printf (sd, "No interrupt generator numbered %d, ignoring.\n", num);
|
|
}
|
|
}
|
|
else if (*argv && !strcmp (*argv, "info"))
|
|
{
|
|
if (intgen_list)
|
|
{
|
|
for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
|
|
sim_io_printf (sd, "Interrupt generator %d (%s) at pc=0x%lx/time=%ld%s.\n",
|
|
intgen->number,
|
|
interrupt_names[intgen->type],
|
|
(long) intgen->address,
|
|
intgen->time,
|
|
(intgen->enabled ? "" : " (disabled)"));
|
|
}
|
|
else
|
|
{
|
|
sim_io_printf (sd, "No interrupt generators defined.\n");
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
sim_io_printf (sd, "Invalid interrupt command, must be one of `add', `remove', or `info'.\n");
|
|
}
|
|
/* Cache the presence of a non-maskable generator. */
|
|
have_nm_generator = 0;
|
|
for (intgen = intgen_list; intgen != NULL; intgen = intgen->next)
|
|
{
|
|
if (intgen->type == int_nmi || intgen->type == int_reset)
|
|
{
|
|
have_nm_generator = 1;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
sim_do_command (sd, cmd)
|
|
SIM_DESC sd;
|
|
char *cmd;
|
|
{
|
|
char *mm_cmd = "memory-map";
|
|
char *int_cmd = "interrupt";
|
|
|
|
if (! strncmp (cmd, mm_cmd, strlen (mm_cmd))
|
|
&& strchr (" ", cmd[strlen(mm_cmd)]))
|
|
sim_set_memory_map (sd, cmd + strlen(mm_cmd) + 1);
|
|
|
|
else if (! strncmp (cmd, int_cmd, strlen (int_cmd))
|
|
&& strchr (" ", cmd[strlen(int_cmd)]))
|
|
sim_set_interrupt (sd, cmd + strlen(int_cmd) + 1);
|
|
|
|
else if (! strcmp (cmd, "help"))
|
|
{
|
|
sim_io_printf (sd, "V850 simulator commands:\n\n");
|
|
sim_io_printf (sd, "interrupt add <inttype> { pc | time } <value> -- Set up an interrupt generator\n");
|
|
sim_io_printf (sd, "interrupt remove <n> -- Remove an existing interrupt generator\n");
|
|
sim_io_printf (sd, "interrupt info -- List all the interrupt generators\n");
|
|
sim_io_printf (sd, "memory-map hole=<m>,<n> -- Set the memory map to have a hole between <m> and <n>\n");
|
|
sim_io_printf (sd, "\n");
|
|
}
|
|
else
|
|
sim_io_printf (sd, "\"%s\" is not a valid V850 simulator command.\n",
|
|
cmd);
|
|
}
|