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old-cross-binutils/ld/testsuite/ld-mips-elf/multi-got-1.d
David Daney 7181d6843d 2011-12-09 David Daney <david.daney@cavium.com> 
* ld-mips-elf/tls-multi-got-1.r: Add "0x" to match value for
	MIPS_BASE_ADDRESS.
	* ld-mips-elf/textrel-1.d: Same.
	* ld-mips-elf/multi-got-1.d: Same.
2011-12-10 05:54:45 +00:00

8222 lines
521 KiB
Makefile
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#name: MIPS multi-got-1
#as: -EB -32 -KPIC
#source: multi-got-1-1.s
#source: multi-got-1-2.s
#ld: -melf32btsmip -shared
#readelf: -d -r
Dynamic section at offset .* contains 17 entries:
Tag Type Name/Value
0x00000004 \(HASH\) 0x[0-9a-f]+
0x00000005 \(STRTAB\) 0x[0-9a-f]+
0x00000006 \(SYMTAB\) 0x[0-9a-f]+
0x0000000a \(STRSZ\) [0-9]+ \(bytes\)
0x0000000b \(SYMENT\) 16 \(bytes\)
0x00000003 \(PLTGOT\) 0x[0-9a-f]+
0x00000011 \(REL\) 0x[0-9a-f]+
0x00000012 \(RELSZ\) 65544 \(bytes\)
0x00000013 \(RELENT\) 8 \(bytes\)
0x70000001 \(MIPS_RLD_VERSION\) 1
0x70000005 \(MIPS_FLAGS\) NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) 0x0
0x7000000a \(MIPS_LOCAL_GOTNO\) 2
0x70000011 \(MIPS_SYMTABNO\) [0-9]+
0x70000012 \(MIPS_UNREFEXTNO\) [0-9]+
0x70000013 \(MIPS_GOTSYM\) 0x[0-9a-f]+
0x00000000 \(NULL\) 0x0
Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains 8193 entries:
Offset Info Type Sym.Value Sym. Name
00000000 00000000 R_MIPS_NONE
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
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^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
^[0-9a-f]+ [0-9a-f]+ R_MIPS_REL32 [0-9a-f]+ sym_2_[0-9]+
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