8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
430 lines
10 KiB
C
430 lines
10 KiB
C
/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998-2013 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sim-main.h"
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#include "hw-main.h"
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/* DEVICE
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mn103cpu - mn10300 cpu virtual device
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DESCRIPTION
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Implements the external mn10300 functionality. This includes the
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delivery of interrupts generated from other devices and the
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handling of device specific registers.
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PROPERTIES
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reg = <address> <size>
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Specify the address of the mn10300's control register block. This
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block contains the Interrupt Vector Registers.
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The reg property value `0x20000000 0x42' locates the register block
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at the address specified in the mn10300 user guide.
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PORTS
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reset (input)
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Currently ignored.
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nmi (input)
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Deliver a non-maskable interrupt to the processor.
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level (input)
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Maskable interrupt level port port. The interrupt controller
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notifies the processor of any change in the level of pending
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requested interrupts via this port.
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ack (output)
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Output signal indicating that the processor is delivering a level
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interrupt. The value passed with the event specifies the level of
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the interrupt being delivered.
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BUGS
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When delivering an interrupt, this code assumes that there is only
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one processor (number 0).
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This code does not attempt to be efficient at handling pending
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interrupts. It simply schedules the interrupt delivery handler
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every instruction cycle until all pending interrupts go away. An
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alternative implementation might modify instructions that change
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the PSW and have them check to see if the change makes an interrupt
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delivery possible.
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*/
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/* The interrupt vectors */
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enum { NR_VECTORS = 7, };
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/* The interrupt controller register address blocks */
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struct mn103cpu_block {
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unsigned_word base;
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unsigned_word bound;
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};
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struct mn103cpu {
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struct mn103cpu_block block;
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struct hw_event *pending_handler;
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int pending_level;
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int pending_nmi;
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int pending_reset;
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/* the visible registers */
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unsigned16 interrupt_vector[NR_VECTORS];
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unsigned16 internal_memory_control;
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unsigned16 cpu_mode;
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};
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/* input port ID's */
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enum {
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RESET_PORT,
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NMI_PORT,
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LEVEL_PORT,
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};
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/* output port ID's */
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enum {
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ACK_PORT,
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};
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static const struct hw_port_descriptor mn103cpu_ports[] = {
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/* interrupt inputs */
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{ "reset", RESET_PORT, 0, input_port, },
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{ "nmi", NMI_PORT, 0, input_port, },
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{ "level", LEVEL_PORT, 0, input_port, },
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/* interrupt ack (latch) output from cpu */
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{ "ack", ACK_PORT, 0, output_port, },
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{ NULL, },
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method mn103cpu_io_read_buffer;
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static hw_io_write_buffer_method mn103cpu_io_write_buffer;
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static hw_port_event_method mn103cpu_port_event;
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static void
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attach_mn103cpu_regs (struct hw *me,
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struct mn103cpu *controller)
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{
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unsigned_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space,
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&attach_address,
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me);
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controller->block.base = attach_address;
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hw_unit_size_to_attach_size (hw_parent (me),
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®.size,
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&attach_size, me);
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controller->block.bound = attach_address + (attach_size - 1);
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if ((controller->block.base & 3) != 0)
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hw_abort (me, "cpu register block must be 4 byte aligned");
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hw_attach_address (hw_parent (me),
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0,
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attach_space, attach_address, attach_size,
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me);
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}
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static void
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mn103cpu_finish (struct hw *me)
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{
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struct mn103cpu *controller;
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controller = HW_ZALLOC (me, struct mn103cpu);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, mn103cpu_io_read_buffer);
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set_hw_io_write_buffer (me, mn103cpu_io_write_buffer);
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set_hw_ports (me, mn103cpu_ports);
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set_hw_port_event (me, mn103cpu_port_event);
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/* Attach ourself to our parent bus */
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attach_mn103cpu_regs (me, controller);
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/* Initialize the read-only registers */
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controller->pending_level = 7; /* FIXME */
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/* ... */
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}
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/* An event arrives on an interrupt port */
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static void
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deliver_mn103cpu_interrupt (struct hw *me,
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void *data)
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{
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struct mn103cpu *controller = hw_data (me);
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SIM_DESC simulator = hw_system (me);
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sim_cpu *cpu = STATE_CPU (simulator, 0);
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if (controller->pending_reset)
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{
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controller->pending_reset = 0;
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/* need to clear all registers et.al! */
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HW_TRACE ((me, "Reset!"));
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hw_abort (me, "Reset!");
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}
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else if (controller->pending_nmi)
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{
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controller->pending_nmi = 0;
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store_word (SP - 4, CIA_GET (cpu));
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store_half (SP - 8, PSW);
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PSW &= ~PSW_IE;
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SP = SP - 8;
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CIA_SET (cpu, 0x40000008);
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HW_TRACE ((me, "nmi pc=0x%08lx psw=0x%04x sp=0x%08lx",
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(long) CIA_GET (cpu), (unsigned) PSW, (long) SP));
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}
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else if ((controller->pending_level < EXTRACT_PSW_LM)
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&& (PSW & PSW_IE))
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{
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/* Don't clear pending level. Request continues to be pending
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until the interrupt controller clears/changes it */
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store_word (SP - 4, CIA_GET (cpu));
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store_half (SP - 8, PSW);
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PSW &= ~PSW_IE;
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PSW &= ~PSW_LM;
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PSW |= INSERT_PSW_LM (controller->pending_level);
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SP = SP - 8;
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CIA_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]);
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HW_TRACE ((me, "port-out ack %d", controller->pending_level));
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hw_port_event (me, ACK_PORT, controller->pending_level);
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HW_TRACE ((me, "int level=%d pc=0x%08lx psw=0x%04x sp=0x%08lx",
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controller->pending_level,
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(long) CIA_GET (cpu), (unsigned) PSW, (long) SP));
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}
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if (controller->pending_level < 7) /* FIXME */
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{
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/* As long as there is the potential need to deliver an
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interrupt we keep rescheduling this routine. */
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if (controller->pending_handler != NULL)
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controller->pending_handler =
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hw_event_queue_schedule (me, 1, deliver_mn103cpu_interrupt, NULL);
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}
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else
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{
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/* Don't bother re-scheduling the interrupt handler as there is
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nothing to deliver */
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controller->pending_handler = NULL;
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}
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}
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static void
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mn103cpu_port_event (struct hw *me,
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int my_port,
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struct hw *source,
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int source_port,
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int level)
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{
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struct mn103cpu *controller = hw_data (me);
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/* Schedule our event handler *now* */
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if (controller->pending_handler == NULL)
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controller->pending_handler =
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hw_event_queue_schedule (me, 0, deliver_mn103cpu_interrupt, NULL);
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switch (my_port)
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{
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case RESET_PORT:
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controller->pending_reset = 1;
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HW_TRACE ((me, "port-in reset"));
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break;
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case NMI_PORT:
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controller->pending_nmi = 1;
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HW_TRACE ((me, "port-in nmi"));
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break;
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case LEVEL_PORT:
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controller->pending_level = level;
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HW_TRACE ((me, "port-in level=%d", level));
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break;
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default:
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hw_abort (me, "bad switch");
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break;
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}
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}
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/* Read/write to a CPU register */
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enum mn103cpu_regs {
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INVALID_REG,
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IVR0_REG,
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IVR1_REG,
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IVR2_REG,
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IVR3_REG,
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IVR4_REG,
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IVR5_REG,
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IVR6_REG,
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IMCR_REG,
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CPUM_REG,
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};
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static enum mn103cpu_regs
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decode_mn103cpu_addr (struct hw *me,
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struct mn103cpu *controller,
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unsigned_word base)
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{
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switch (base - controller->block.base)
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{
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case 0x000: return IVR0_REG;
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case 0x004: return IVR1_REG;
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case 0x008: return IVR2_REG;
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case 0x00c: return IVR3_REG;
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case 0x010: return IVR4_REG;
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case 0x014: return IVR5_REG;
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case 0x018: return IVR6_REG;
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case 0x020: return IMCR_REG;
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case 0x040: return CPUM_REG;
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default: return INVALID_REG;
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}
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}
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static unsigned
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mn103cpu_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct mn103cpu *controller = hw_data (me);
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unsigned16 val = 0;
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enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base);
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switch (reg)
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{
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case IVR0_REG:
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case IVR1_REG:
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case IVR2_REG:
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case IVR3_REG:
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case IVR4_REG:
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case IVR5_REG:
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case IVR6_REG:
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val = controller->interrupt_vector[reg - IVR0_REG];
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break;
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case IMCR_REG:
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val = controller->internal_memory_control;
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break;
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case CPUM_REG:
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val = controller->cpu_mode;
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break;
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default:
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/* just ignore the read */
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break;
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}
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if (nr_bytes == 2)
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*(unsigned16*) dest = H2LE_2 (val);
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return nr_bytes;
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}
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static unsigned
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mn103cpu_io_write_buffer (struct hw *me,
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const void *source,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct mn103cpu *controller = hw_data (me);
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unsigned16 val;
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enum mn103cpu_regs reg;
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if (nr_bytes != 2)
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hw_abort (me, "must be two byte write");
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reg = decode_mn103cpu_addr (me, controller, base);
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val = LE2H_2 (* (unsigned16 *) source);
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switch (reg)
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{
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case IVR0_REG:
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case IVR1_REG:
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case IVR2_REG:
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case IVR3_REG:
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case IVR4_REG:
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case IVR5_REG:
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case IVR6_REG:
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controller->interrupt_vector[reg - IVR0_REG] = val;
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HW_TRACE ((me, "ivr%d = 0x%04lx", reg - IVR0_REG, (long) val));
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break;
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default:
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/* just ignore the write */
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break;
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}
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return nr_bytes;
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}
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const struct hw_descriptor dv_mn103cpu_descriptor[] = {
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{ "mn103cpu", mn103cpu_finish, },
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{ NULL },
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};
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